diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-05 22:48:41 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-10 02:27:40 +0000 |
| commit | 0bae5a72c52a7e696a3859a88c78372e5cb394b4 (patch) | |
| tree | 2ee0b0e63e54a41aef0820acde3a7ae0329e662c /src/mainboard/supermicro/x11-lga1151-series | |
| parent | fb7a06b5b77db178050237671d1da5a3942f4b54 (diff) | |
mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devices
Add the subsystem ids to PCI ports and devices, which were dumped on
vendor firmware using `lspci`.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Idb36c5c72e1b0b8303439ae5dce772822f551d2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48368
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro/x11-lga1151-series')
| -rw-r--r-- | src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index a03ecc5eba..549d7d27a3 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -44,6 +44,7 @@ chip soc/intel/skylake register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" device domain 0 on + subsystemid 0x15d9 0x0896 inherit device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" end @@ -63,12 +64,16 @@ chip soc/intel/skylake device pci 1d.0 on # PCH PCIe Port 9 register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" - device pci 00.0 on end # GbE 1 + device pci 00.0 on # GbE 1 + subsystemid 0x15d9 0x1533 + end end device pci 1d.1 on # PCH PCIe Port 10 register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "1" - device pci 00.1 on end # GbE 2 + device pci 00.0 on # GbE 2 + subsystemid 0x15d9 0x1533 + end end device pci 1d.2 on # PCH PCIe Port 11 register "PcieRpEnable[10]" = "1" |