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author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-24 21:41:35 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-29 16:30:50 +0000 |
commit | fc709fee099b4035e0f5311a401cda886ad0d8a2 (patch) | |
tree | 6512838bda8f1d20ac3381c305ba7b9f85150ae0 /src/mainboard/supermicro/x11-lga1151-series/variants | |
parent | 7d8c832d1fa9fca354f93571bf0c4b8905de86d8 (diff) |
soc/amd/stoneyridge: use common AMD CPU power state ACPI generation
Instead of using the PSTATE SSDT generated by binaryPI, use the common
AMD code by selecting SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE. To
match the SSDT from binaryPI, set ACPI_SSDT_PSD_INDEPENDENT to n. There
are two differences to the binaryPI SSDT: Now coreboot includes the C1
state in the _CST package instead of just having the kernel add this due
to the ACPI_FADT_C1_SUPPORTED bit being set and the address of the
PS_STS_REG P state status MSR is written to the corresponding field of
the _PCT package instead of being 0.
TEST=On Careena the new P and C state ACPI packages are nearly identical
to the ones from the SSDT from binaryPI with the two functional
differences mentioned above.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icdf6bc8f0e0363f185a294ab84edcb51322e7eb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/supermicro/x11-lga1151-series/variants')
0 files changed, 0 insertions, 0 deletions