diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-24 01:23:28 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-28 12:57:51 +0000 |
| commit | ddd44f4fe9f45dfcdb2467073b4faf1fdb03ce47 (patch) | |
| tree | b29f7c11360e2d85945960277da46181c83c01fc /src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb | |
| parent | 84fde762e7c4e1a8e43194a9444b10b681e1cb50 (diff) | |
mb/supermicro/x11-lga1151-series: restructure and clean up devicetree
Drop zero-value devicetree options and move PcieRpEnable options down to
the corresponding devices.
Test: built with TIMELESS=1; binaries remain identical
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9285d786e973621a732e2627c734adc930e54207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb')
| -rw-r--r-- | src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 8b0a2a0bd1..d7f187356f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -11,13 +11,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x007c0a01" # Super IO SWC register "gen2_dec" = "0x000c0ca1" # IPMI KCS - # PCIe configuration - register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 - register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5 - register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1 - register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2 - register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA - # USB configuration # USB0/1 register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" @@ -58,18 +51,23 @@ chip soc/intel/skylake smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X" end device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) + register "PcieRpEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) + register "PcieRpEnable[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device pci 1d.0 on # PCH PCIe Port 9 + register "PcieRpEnable[8]" = "1" device pci 00.0 on end # GbE 1 end device pci 1d.1 on # PCH PCIe Port 10 + register "PcieRpEnable[9]" = "1" device pci 00.1 on end # GbE 2 end device pci 1d.2 on # PCH PCIe Port 11 + register "PcieRpEnable[10]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end |