diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-26 21:40:49 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-04 12:24:56 +0000 |
| commit | fe6526512a742c0bac2c1bbc919ee143ade3be06 (patch) | |
| tree | 311caf1ebb02b46761c8cfcee4c959ff37dcf377 /src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf | |
| parent | aaf5b09a5adb5ee21b504bcf07145fd977000d86 (diff) | |
mb/supermicro/x11ssh-tf: Drop `PcieRpClkReqSupport` lines
They default to zero already, so we might as well drop them.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I3c04240b270f51d584f879e1344301679f133fdb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43928
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf')
| -rw-r--r-- | src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 50767bb35e..7996791a69 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -14,19 +14,15 @@ chip soc/intel/skylake # PCIe configuration # Enable JPCIE1 register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "0" # Enable ASpeed PCI bridge register "PcieRpEnable[2]" = "1" - register "PcieRpClkReqSupport[2]" = "0" # Enable X550T (10GbE) register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "0" # Enable M.2 register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "0" # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" |