diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-10-23 09:01:05 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2023-11-16 13:19:16 +0000 |
| commit | a03999be254561868003a61b3f1e8bc6e9fe6326 (patch) | |
| tree | b3c1d7e2899ee4be4f7644395f7f3a76358da2bb /src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf | |
| parent | 7713a2f295d9ed9a7023a78e085ce190ee1203fe (diff) | |
mb/supermicro/x11: Make use of chipset devicetree
Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78594
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf')
| -rw-r--r-- | src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 56b8f9ce7b..b46b2205b8 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -40,30 +40,32 @@ chip soc/intel/skylake }" device domain 0 on - device pci 01.0 on end # unused - device pci 01.1 on # PCIE Slot (JPCIE1) + device ref peg0 on end # unused + device ref peg1 on + # Slot JPCIE1 register "PcieRpEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" end - device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1) + device ref pcie_rp1 on + # Slot JPCIE1 register "PcieRpEnable[2]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" end - device pci 1c.2 on # PCI Express Port 3 + device ref pcie_rp3 on device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end end - device pci 1c.4 on # PCI Express Port 5 + device ref pcie_rp5 on register "PcieRpEnable[4]" = "1" device pci 00.0 on end # 10GbE device pci 00.1 on end # 10GbE end - device pci 1d.0 on # PCI Express Port 9 + device ref pcie_rp9 on register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end - device pci 1f.0 on # LPC Interface + device ref lpc_espi on chip drivers/ipmi use pch_gpio as gpio_dev register "post_complete_gpio" = "GPP_B20" |