diff options
| author | Tristan Corrick <tristan@corrick.kiwi> | 2019-04-24 01:24:30 +1200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-25 15:52:03 +0000 |
| commit | 478a1212ef0725fe86c59527f5aa30be5606c329 (patch) | |
| tree | f707174b9194f246a8275e89f4978b839abd0414 /src/mainboard/supermicro/x10slm-f/romstage.c | |
| parent | 5849b14705a2994f8386a265998d415b01c43996 (diff) | |
mb/supermicro/x10slm-f: Do SIO setup in bootblock
Lynx Point switched to doing mainboard-specific super I/O setup in the
bootblock with commit d893a2635fdd ("sb/intel/lynxpoint: Enable LPC/SIO
setup in bootblock"). The X10SLM+-F was added while that commit was in
review, and hence did not receive the necessary changes to SIO setup.
This patch has not been tested on hardware.
Change-Id: I7a648ec967dea2113cbbde1a93c1963ca6dd3c88
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/supermicro/x10slm-f/romstage.c')
| -rw-r--r-- | src/mainboard/supermicro/x10slm-f/romstage.c | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 84ad047725..e43302af24 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -17,14 +17,11 @@ #include <cpu/intel/haswell/haswell.h> #include <cpu/intel/romstage.h> -#include <device/pnp_ops.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/pei_data.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h> #include <stdint.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6776/nct6776.h> static const struct rcba_config_instruction rcba_config[] = { RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), @@ -41,27 +38,6 @@ static const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_config_superio(void) -{ - const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); - const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); - const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); - - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); - - /* Select HWM/LED functions instead of floppy functions. */ - pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); - pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); - - /* Power RAM in S3 and let the PCH handle power failure actions. */ - pnp_set_logical_device(ACPI_DEV); - pnp_write_config(ACPI_DEV, 0xe4, 0x70); - - nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); -} - void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { |