diff options
| author | efdesign98 <efdesign98@gmail.com> | 2011-07-20 12:37:58 -0600 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2011-07-22 00:20:59 +0200 |
| commit | 00c8c4a31632150fa711493f39e727da950ebe9f (patch) | |
| tree | f3bad2e78ddb6999ad551a73f05c049a266a14ab /src/mainboard/supermicro/h8scm_fam10/mainboard.c | |
| parent | 09ea8ea1a74d56a37755cec52077555b91f9e5b4 (diff) | |
Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro/h8scm_fam10/mainboard.c')
| -rwxr-xr-x[-rw-r--r--] | src/mainboard/supermicro/h8scm_fam10/mainboard.c | 37 |
1 files changed, 2 insertions, 35 deletions
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index e6ed22b1a0..90b53357ad 100644..100755 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -29,9 +29,6 @@ #include <southbridge/amd/sr5650/cmn.h> #include "chip.h" -#define SMBUS_IO_BASE 0x6000 - -uint64_t uma_memory_base, uma_memory_size; void set_pcie_reset(void); void set_pcie_dereset(void); @@ -95,47 +92,17 @@ static void h8scm_enable(device_t dev) printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", __func__, msr2.lo, msr2.hi); -#if (CONFIG_GFXUMA == 1) - - /* refer to UMA Size Consideration in 780 BDG. */ - switch (msr.lo) { - case 0x10000000: /* 256M system memory */ - uma_memory_size = 0x4000000; /* 64M recommended UMA */ - break; - - case 0x20000000: /* 512M system memory */ - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - break; - - default: /* 1GB and above system memory */ - uma_memory_size = 0x10000000; /* 256M recommended UMA */ - break; - } -#else - /* TODO: TOP_MEM2 */ - uma_memory_size = 0;//0x8000000; /* 128M recommended UMA */ -#endif - uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ - printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); set_pcie_dereset(); /* get_ide_dma66(); */ } +#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1) int add_mainboard_resources(struct lb_memory *mem) { - /* UMA is removed from system memory in the northbridge code, but - * in some circumstances we want the memory mentioned as reserved. - */ -#if (CONFIG_GFXUMA == 1) - printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", - uma_memory_base, uma_memory_size); - lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, - uma_memory_size); -#endif return 0; } +#endif struct chip_operations mainboard_ops = { CHIP_NAME("AMD H8SCM Mainboard") |