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authorZheng Bao <zheng.bao@amd.com>2011-03-28 04:38:14 +0000
committerZheng Bao <Zheng.Bao@amd.com>2011-03-28 04:38:14 +0000
commit910f4ca5c50ef9d1d05c46b3ff52c69d29f745dd (patch)
tree486b0b60dcfb8bb63509da176c7b9986140ef5db /src/mainboard/supermicro/h8scm_fam10/Kconfig
parentd3de3eed7b64ac2a8e37a7c7eec13f76965ff97c (diff)
Add support for Supermicro H8scm.
It is AMD C32 + SR5650 + SP5100. It is created by svn copy amd/tilapia_fam10. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro/h8scm_fam10/Kconfig')
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/Kconfig89
1 files changed, 89 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig
new file mode 100644
index 0000000000..e0547ab5f4
--- /dev/null
+++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig
@@ -0,0 +1,89 @@
+if BOARD_SUPERMICRO_H8SCM_FAM10
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_AMD_SOCKET_C32
+ select DIMM_DDR3
+ select DIMM_REGISTERED
+ select NORTHBRIDGE_AMD_AMDFAM10
+ select SOUTHBRIDGE_AMD_SR5650
+ select SOUTHBRIDGE_AMD_SP5100
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
+ select GENERATE_PIRQ_TABLE
+ select GENERATE_MP_TABLE
+ select HAVE_MAINBOARD_RESOURCES
+ select HAVE_HARD_RESET
+ select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ select LIFT_BSP_APIC_ID
+ select SERIAL_CPU_INIT
+ select AMDMCT
+ select GENERATE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_2048
+ select RAMINIT_SYSINFO
+ select ENABLE_APIC_EXT_ID
+ select GFXUMA
+
+config MAINBOARD_DIR
+ string
+ default supermicro/h8scm_fam10
+
+config APIC_ID_OFFSET
+ hex
+ default 0x0
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "H8SCM (Fam10)"
+
+config MAX_CPUS
+ int
+ default 16
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 1
+
+config MEM_TRAIN_SEQ
+ int
+ default 2
+
+config SB_HT_CHAIN_ON_BUS0
+ int
+ default 1
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x1
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0x0
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config AMD_UCODE_PATCH_FILE
+ string
+ default "mc_patch_010000c4.h"
+
+config RAMTOP
+ hex
+ default 0x2000000
+
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
+config ACPI_SSDTX_NUM
+ int
+ default 0
+
+config RAMBASE
+ hex
+ default 0x200000
+
+endif # BOARD_AMD_H8SCM_FAM10