mb/*/*: Drop AMDFAM10 mainboards

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

12 files changed, 0 insertions, 1279 deletions

diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig
deleted file mode 100644
index 55d1153c7b..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-if BOARD_SUPERMICRO_H8QME_FAM10
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_SOCKET_F_1207
-	select DIMM_DDR2
-	select DIMM_REGISTERED
-	select NORTHBRIDGE_AMD_AMDFAM10
-	select SOUTHBRIDGE_AMD_AMD8132
-	select SOUTHBRIDGE_NVIDIA_MCP55
-	select HT_CHAIN_DISTRIBUTE
-	select SUPERIO_WINBOND_W83627HF
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select LIFT_BSP_APIC_ID
-	select BOARD_ROMSIZE_KB_1024
-	select ENABLE_APIC_EXT_ID
-
-config MAINBOARD_DIR
-	string
-	default supermicro/h8qme_fam10
-
-config DCACHE_RAM_BASE
-	hex
-	default 0xc4000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x0c000
-
-config APIC_ID_OFFSET
-	hex
-	default 0x0
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "H8QME-2+ (Fam10)"
-
-config MAX_CPUS
-	int
-	default 16
-
-config MAX_PHYSICAL_CPUS
-	int
-	default 4
-
-config HT_CHAIN_END_UNITID_BASE
-	hex
-	default 0x20
-
-config HT_CHAIN_UNITID_BASE
-	hex
-	default 0x1
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-endif # BOARD_SUPERMICRO_H8QME_FAM10
diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig.name b/src/mainboard/supermicro/h8qme_fam10/Kconfig.name
deleted file mode 100644
index d7f1933d60..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_SUPERMICRO_H8QME_FAM10
-	bool "H8QME-2+ (Fam10)"
diff --git a/src/mainboard/supermicro/h8qme_fam10/Makefile.inc b/src/mainboard/supermicro/h8qme_fam10/Makefile.inc
deleted file mode 100644
index 91d4b39c32..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += resourcemap.c
-
-ramstage-y += get_bus_conf.c
diff --git a/src/mainboard/supermicro/h8qme_fam10/board_info.txt b/src/mainboard/supermicro/h8qme_fam10/board_info.txt
deleted file mode 100644
index cb3000fd04..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: server
-Board URL: http://www.supermicro.com/Aplus/motherboard/Opteron8000/MCP55/H8QME-2.cfm
diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout
deleted file mode 100644
index 331e0162bb..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout
+++ /dev/null
@@ -1,102 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-393          3       r       0        unused
-#394         7       unused
-401          1       e       1        interleave_chip_selects
-402          1       e       1        interleave_nodes
-403          1       e       1        interleave_memory_channels
-404          2       e       8        max_mem_clock
-406          1       e       2        multi_core
-412          4       e       6        debug_level
-416          5       e       10       ecc_scrub_rate
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        gart
-446          1       e       1        power_on_after_fail
-456          1       e       1        ECC_memory
-457          1       e       1        ECC_redirection
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     0     Emergency
-6     1     Alert
-6     2     Critical
-6     3     Error
-6     4     Warning
-6     5     Notice
-6     6     Information
-6     7     Debug
-6     8     Spew
-8     0     DDR2-800
-8     1     DDR2-667
-8     2     DDR2-533
-8     3     DDR2-400
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-10    0     Disabled
-10    1     40ns
-10    2     80ns
-10    3     160ns
-10    4     320ns
-10    5     640ns
-10    6     1.28us
-10    7     2.56us
-10    8     5.12us
-10    9     10.2us
-10    10    20.5us
-10    11    41us
-10    12    81.9us
-10    13    163.8us
-10    14    327.7us
-10    15    655.4us
-10    16    1.31ms
-10    17    2.62ms
-10    18    5.24ms
-10    19    10.49ms
-10    20    20.97sms
-10    21    42ms
-10    22    84ms
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
deleted file mode 100644
index 317d643d9a..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
+++ /dev/null
@@ -1,115 +0,0 @@
-chip northbridge/amd/amdfam10/root_complex	# Root complex
-	device cpu_cluster 0 on			# (L)APIC cluster
-		chip cpu/amd/socket_F_1207	# CPU socket
-			device lapic 0 on end	# Local APIC of the CPU
-		end
-	end
-	device domain 0 on			# PCI domain
-		subsystemid 0x15d9 0x1511 inherit
-		chip northbridge/amd/amdfam10	# Northbridge / RAM controller
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.0 on	# SB on link 2
-				chip southbridge/nvidia/mcp55		# Southbridge
-					device pci 0.0 on end			# HT
-					device pci 1.0 on			# LPC
-						chip superio/winbond/w83627hf	# Super I/O
-							device pnp 2e.0 off	# Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off	# Parallel port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on	# Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 off	# Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.5 on	# PS/2 keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-								irq 0x72 = 12
-							end
-							device pnp 2e.6 off	# SFI
-								io 0x62 = 0x100
-							end
-							device pnp 2e.7 off	# GPIO, game port, MIDI
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end
-							device pnp 2e.8 off end	# WDTO PLED
-							device pnp 2e.9 off end	# GPIO SUSLED
-							device pnp 2e.a off end	# ACPI
-							device pnp 2e.b on	# Hardware monitor
-								io 0x60 = 0x290
-								irq 0x70 = 5
-							end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.1 on			# SM 1
-						# PCI device SMBus address will
-						# depend on addon PCI device, do
-						# we need to scan_smbus_bus?
-						chip drivers/generic/generic	# MAC EEPROM
-							device i2c 51 on end
-						end
-					end
-					device pci 2.0 on end	# USB 1.1
-					device pci 2.1 on end	# USB 2
-					device pci 4.0 on end	# IDE
-					device pci 5.0 on end	# SATA 0
-					device pci 5.1 on end	# SATA 1
-					device pci 5.2 on end	# SATA 2
-					device pci 6.1 off end	# AZA
-					device pci 7.0 on
-						device pci 1.0 on end
-					end
-					device pci 8.0 off end
-					device pci 9.0 off end
-					device pci a.0 on end	# PCI E 5
-					device pci b.0 on end	# PCI E 4
-					device pci c.0 on end	# PCI E 3
-					device pci d.0 on end	# PCI E 2
-					device pci e.0 on end	# PCI E 1
-					device pci f.0 on end	# PCI E 0
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "sata1_enable" = "1"
-					# 1: SMBus under 2e.8, 2: SM0 3: SM1
-					register "mac_eeprom_smbus" = "3"
-					register "mac_eeprom_addr" = "0x51"
-				end
-			end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.0 on
-				chip southbridge/amd/amd8132
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on
-						device pci 3.0 on end
-						device pci 3.1 on end
-					end
-					device pci 1.1 on end
-				end
-			end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-			device pci 19.4 on end
-		end
-	end
-end
diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
deleted file mode 100644
index 56ea43c7fe..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdfam10_sysconf.h>
-
-#include <stdlib.h>
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-unsigned int sbdn3;
-
-void get_bus_conf(void)
-{
-
-	unsigned int apicid_base;
-	struct mb_sysconf_t *m;
-
-	struct device *dev;
-	int i;
-
-	sysconf.mb = &mb_sysconf;
-
-	m = sysconf.mb;
-	memset(m, 0, sizeof(struct mb_sysconf_t));
-
-	get_default_pci1234(32);
-
-	sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
-	m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
-
-	m->bus_8132_0 = (sysconf.pci1234[1] >> 12) & 0xff;
-	sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain
-
-		/* MCP55 */
-		dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
-
-		if (dev) {
-			m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		}
-		else {
-			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
-		}
-
-		for(i = 2; i < 8; i++) {
-			dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0));
-			if (dev) {
-				m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-			}
-			else {
-				printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2);
-			}
-		}
-
-		/* 8132_1 */
-
-		dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3, 0));
-		m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		m->bus_8132_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-		m->bus_8132_2++;
-
-		/* 8132_2 */
-		dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3 + 1, 0));
-		m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-/*I/O APICs:	APIC ID	Version	State		Address*/
-	if (CONFIG(LOGICAL_CPUS))
-		apicid_base = get_apicid_base(3);
-	else
-		apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
-	m->apicid_mcp55 = apicid_base+0;
-	m->apicid_8132_1 = apicid_base+1;
-	m->apicid_8132_2 = apicid_base+2;
-}
diff --git a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c
deleted file mode 100644
index b77e86209b..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdfam10_sysconf.h>
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
-			    uint8_t devfn, uint8_t link0, uint16_t bitmap0,
-			    uint8_t link1, uint16_t bitmap1, uint8_t link2,
-			    uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
-			    uint8_t slot, uint8_t rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	unsigned int slot_num;
-	uint8_t *v;
-	struct mb_sysconf_t *m;
-	unsigned int sbdn;
-
-	uint8_t sum = 0;
-	int i;
-
-	sbdn = sysconf.sbdn;
-	m = sysconf.mb;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (uint8_t *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = m->bus_mcp55[0];
-	pirq->rtr_devfn = PCI_DEVFN(sbdn + 6, 0);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x10de;
-	pirq->rtr_device = 0x0364;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-//pci bridge
-	write_pirq_info(pirq_info, m->bus_mcp55[0], PCI_DEVFN(sbdn + 6, 0), 0x1,
-			0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
-	pirq_info++;
-	slot_num++;
-
-	for (i = 1; i < sysconf.hc_possible_num; i++) {
-		if (!(sysconf.pci1234[i] & 0x1))
-			continue;
-		unsigned int busn = (sysconf.pci1234[i] >> 12) & 0xff;
-		unsigned int devn = sysconf.hcdn[i] & 0xff;
-
-		write_pirq_info(pirq_info, busn, PCI_DEVFN(devn, 0), 0x1, 0x4ca0,
-				0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
-		pirq_info++;
-		slot_num++;
-	}
-
-#if CONFIG_CBB
-	write_pirq_info(pirq_info, CONFIG_CBB, PCI_DEVFN(0, 0), 0x1, 0x4ca0, 0x2,
-			0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
-	pirq_info++;
-	slot_num++;
-	if (sysconf.nodes > 32) {
-		write_pirq_info(pirq_info, CONFIG_CBB - 1, PCI_DEVFN(0, 0), 0x1,
-				0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0,
-				0, 0);
-		pirq_info++;
-		slot_num++;
-	}
-#endif
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "done.\n");
-
-	return (unsigned long)pirq_info;
-
-}
diff --git a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
deleted file mode 100644
index f93f9e8380..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef MB_SYSCONF_H
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
-	unsigned char bus_mcp55[8]; //1
-	unsigned int apicid_mcp55;
-
-	unsigned char bus_8132_0;  //7
-	unsigned char bus_8132_1;  //8
-	unsigned char bus_8132_2;  //9
-	unsigned int apicid_8132_1;
-	unsigned int apicid_8132_2;
-};
-
-#endif
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
deleted file mode 100644
index 7e6237f1f6..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <stdint.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-#include "mb_sysconf.h"
-
-extern unsigned int sbdn3;
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	struct mb_sysconf_t *m;
-	unsigned int sbdn;
-	int i, j, bus_isa;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-
-	sbdn = sysconf.sbdn;
-	m = sysconf.mb;
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-/*I/O APICs:	APIC ID	Version	State		Address*/
-	{
-		struct device *dev;
-		struct resource *res;
-		uint32_t dword;
-
-		dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
-		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_1);
-			if (res) {
-				smp_write_ioapic(mc, m->apicid_mcp55, 0x11,
-						 res2mmio(res, 0, 0));
-			}
-
-			dword = 0x00000ab5;
-			pci_write_config32(dev, 0x7c, dword);
-
-			dword = 0x5ab0a500;
-			pci_write_config32(dev, 0x80, dword);
-
-			dword = 0xa000000b;
-			pci_write_config32(dev, 0x84, dword);
-
-		}
-
-
-	}
-
-	mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
-
-		   /*I/O Ints:	Type	Polarity    Trigger			Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0x5);  /*  5 SMBus, OK */
-	smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0xb); /* 11 USB, OK */
-	smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0xa); /* 10 USB, OK */
-	smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x5); /*  5  IDE, OK*/
-	smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
-	smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
-	smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 6, 1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/
-
-	smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 3, 0, m->apicid_mcp55, 0x5); /* 5  eth0, OK*/
-	smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 3, 1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
-
-	for(j = 7;j >= 2; j--) {
-		if(!m->bus_mcp55[j]) continue;
-		for(i = 0; i < 4; i++) {
-			smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
-		}
-	}
-
-	for(j = 0; j < 1; j++)
-		for(i = 0; i < 4; i++) {
-			smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
-		}
-
-/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	mptable_lintsrc(mc, bus_isa);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
deleted file mode 100644
index 2398ba25d7..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <commonlib/helpers.h>
-#include <northbridge/amd/amdfam10/amdfam10.h>
-
-void setup_mb_resource_map(void)
-{
-	static const unsigned int register_values[] = {
-		/* Careful set limit registers before base registers which contain the enables */
-		/* DRAM Limit i Registers
-		 * F1:0x44 i = 0
-		 * F1:0x4C i = 1
-		 * F1:0x54 i = 2
-		 * F1:0x5C i = 3
-		 * F1:0x64 i = 4
-		 * F1:0x6C i = 5
-		 * F1:0x74 i = 6
-		 * F1:0x7C i = 7
-		 * [ 2: 0] Destination Node ID
-		 *	   000 = Node 0
-		 *	   001 = Node 1
-		 *	   010 = Node 2
-		 *	   011 = Node 3
-		 *	   100 = Node 4
-		 *	   101 = Node 5
-		 *	   110 = Node 6
-		 *	   111 = Node 7
-		 * [ 7: 3] Reserved
-		 * [10: 8] Interleave select
-		 *	   specifies the values of A[14:12] to use with interleave enable.
-		 * [15:11] Reserved
-		 * [31:16] DRAM Limit Address i Bits 39-24
-		 *	   This field defines the upper address bits of a 40 bit  address
-		 *	   that define the end of the DRAM region.
-		 */
-		// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10
-		ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
-		ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
-		ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
-		ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
-		ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
-		ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
-		ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
-
-		/* DRAM Base i Registers
-		 * F1:0x40 i = 0
-		 * F1:0x48 i = 1
-		 * F1:0x50 i = 2
-		 * F1:0x58 i = 3
-		 * F1:0x60 i = 4
-		 * F1:0x68 i = 5
-		 * F1:0x70 i = 6
-		 * F1:0x78 i = 7
-		 * [ 0: 0] Read Enable
-		 *	   0 = Reads Disabled
-		 *	   1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *	   0 = Writes Disabled
-		 *	   1 = Writes Enabled
-		 * [ 7: 2] Reserved
-		 * [10: 8] Interleave Enable
-		 *	   000 = No interleave
-		 *	   001 = Interleave on A[12] (2 nodes)
-		 *	   010 = reserved
-		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
-		 *	   100 = reserved
-		 *	   101 = reserved
-		 *	   110 = reserved
-		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
-		 * [15:11] Reserved
-		 * [13:16] DRAM Base Address i Bits 39-24
-		 *	   This field defines the upper address bits of a 40-bit address
-		 *	   that define the start of the DRAM region.
-		 */
-		// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10
-		ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
-		ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
-		ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
-		ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
-		ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
-		ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
-		ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
-
-		/* Memory-Mapped I/O Limit i Registers
-		 * F1:0x84 i = 0
-		 * F1:0x8C i = 1
-		 * F1:0x94 i = 2
-		 * F1:0x9C i = 3
-		 * F1:0xA4 i = 4
-		 * F1:0xAC i = 5
-		 * F1:0xB4 i = 6
-		 * F1:0xBC i = 7
-		 * [ 2: 0] Destination Node ID
-		 *	   000 = Node 0
-		 *	   001 = Node 1
-		 *	   010 = Node 2
-		 *	   011 = Node 3
-		 *	   100 = Node 4
-		 *	   101 = Node 5
-		 *	   110 = Node 6
-		 *	   111 = Node 7
-		 * [ 3: 3] Reserved
-		 * [ 5: 4] Destination Link ID
-		 *	   00 = Link 0
-		 *	   01 = Link 1
-		 *	   10 = Link 2
-		 *	   11 = Reserved
-		 * [ 6: 6] Reserved
-		 * [ 7: 7] Non-Posted
-		 *	   0 = CPU writes may be posted
-		 *	   1 = CPU writes must be non-posted
-		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp address bits of a 40-bit address that
-		 *	   defines the end of a memory-mapped I/O region n
-		 */
-		ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
-		ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
-		ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
-		ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
-		ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
-		ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
-		ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
-//		ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
-
-		/* Memory-Mapped I/O Base i Registers
-		 * F1:0x80 i = 0
-		 * F1:0x88 i = 1
-		 * F1:0x90 i = 2
-		 * F1:0x98 i = 3
-		 * F1:0xA0 i = 4
-		 * F1:0xA8 i = 5
-		 * F1:0xB0 i = 6
-		 * F1:0xB8 i = 7
-		 * [ 0: 0] Read Enable
-		 *	   0 = Reads disabled
-		 *	   1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *	   0 = Writes disabled
-		 *	   1 = Writes Enabled
-		 * [ 2: 2] Cpu Disable
-		 *	   0 = Cpu can use this I/O range
-		 *	   1 = Cpu requests do not use this I/O range
-		 * [ 3: 3] Lock
-		 *	   0 = base/limit registers i are read/write
-		 *	   1 = base/limit registers i are read-only
-		 * [ 7: 4] Reserved
-		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		 *	   This field defines the upper address bits of a 40bit address
-		 *	   that defines the start of memory-mapped I/O region i
-		 */
-		ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
-		ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
-		ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
-		ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
-		ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
-		ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
-		ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
-//		ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
-
-		/* PCI I/O Limit i Registers
-		 * F1:0xC4 i = 0
-		 * F1:0xCC i = 1
-		 * F1:0xD4 i = 2
-		 * F1:0xDC i = 3
-		 * [ 2: 0] Destination Node ID
-		 *	   000 = Node 0
-		 *	   001 = Node 1
-		 *	   010 = Node 2
-		 *	   011 = Node 3
-		 *	   100 = Node 4
-		 *	   101 = Node 5
-		 *	   110 = Node 6
-		 *	   111 = Node 7
-		 * [ 3: 3] Reserved
-		 * [ 5: 4] Destination Link ID
-		 *	   00 = Link 0
-		 *	   01 = Link 1
-		 *	   10 = Link 2
-		 *	   11 = reserved
-		 * [11: 6] Reserved
-		 * [24:12] PCI I/O Limit Address i
-		 *	   This field defines the end of PCI I/O region n
-		 * [31:25] Reserved
-		 */
-// WARD CHANGED
-		ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff020,
-		ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
-		ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
-		ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
-
-		/* PCI I/O Base i Registers
-		 * F1:0xC0 i = 0
-		 * F1:0xC8 i = 1
-		 * F1:0xD0 i = 2
-		 * F1:0xD8 i = 3
-		 * [ 0: 0] Read Enable
-		 *	   0 = Reads Disabled
-		 *	   1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *	   0 = Writes Disabled
-		 *	   1 = Writes Enabled
-		 * [ 3: 2] Reserved
-		 * [ 4: 4] VGA Enable
-		 *	   0 = VGA matches Disabled
-		 *	   1 = matches all address < 64K and where A[9:0] is in the
-		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
-		 * [ 5: 5] ISA Enable
-		 *	   0 = ISA matches Disabled
-		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
-		 *	       from matching agains this base/limit pair
-		 * [11: 6] Reserved
-		 * [24:12] PCI I/O Base i
-		 *	   This field defines the start of PCI I/O region n
-		 * [31:25] Reserved
-		 */
-		// WARD CHANGED
-		ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000033,
-		ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
-		ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
-		ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
-
-		/* Config Base and Limit i Registers
-		 * F1:0xE0 i = 0
-		 * F1:0xE4 i = 1
-		 * F1:0xE8 i = 2
-		 * F1:0xEC i = 3
-		 * [ 0: 0] Read Enable
-		 *	   0 = Reads Disabled
-		 *	   1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *	   0 = Writes Disabled
-		 *	   1 = Writes Enabled
-		 * [ 2: 2] Device Number Compare Enable
-		 *	   0 = The ranges are based on bus number
-		 *	   1 = The ranges are ranges of devices on bus 0
-		 * [ 3: 3] Reserved
-		 * [ 6: 4] Destination Node
-		 *	   000 = Node 0
-		 *	   001 = Node 1
-		 *	   010 = Node 2
-		 *	   011 = Node 3
-		 *	   100 = Node 4
-		 *	   101 = Node 5
-		 *	   110 = Node 6
-		 *	   111 = Node 7
-		 * [ 7: 7] Reserved
-		 * [ 9: 8] Destination Link
-		 *	   00 = Link 0
-		 *	   01 = Link 1
-		 *	   10 = Link 2
-		 *	   11 - Reserved
-		 * [15:10] Reserved
-		 * [23:16] Bus Number Base i
-		 *	   This field defines the lowest bus number in configuration region i
-		 * [31:24] Bus Number Limit i
-		 *	   This field defines the highest bus number in configuration region i
-		 */
-		// WARD CHANGED
-		ADDRMAP_REG(0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
-		ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
-		ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
-		ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
-
-	};
-
-	int max;
-	max = ARRAY_SIZE(register_values);
-	setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
deleted file mode 100644
index 7c489ca8dd..0000000000
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <device/pnp_ops.h>
-#include <device/pci_ops.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <timestamp.h>
-#include <spd.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include <delay.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include <cpu/x86/bist.h>
-#include <cpu/amd/car.h>
-#include <cpu/amd/msr.h>
-#include <southbridge/amd/common/reset.h>
-#include <northbridge/amd/amdfam10/raminit.h>
-#include <northbridge/amd/amdht/ht_wrapper.h>
-#include <cpu/amd/family_10h-family_15h/init_cpus.h>
-#include <arch/early_variables.h>
-#include <cbmem.h>
-#include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN
-
-#include "cpu/amd/quadcore/quadcore.c"
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#define SUPERIO_DEV PNP_DEV(0x2e, 0)
-
-#define SMBUS_SWITCH1 0x70
-#define SMBUS_SWITCH2 0x72
-
-int spd_read_byte(unsigned int device, unsigned int address);
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
-	smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
-}
-
-inline int spd_read_byte(unsigned int device, unsigned int address)
-{
-	return smbus_read_byte(device, address);
-}
-
-unsigned int get_sbdn(unsigned int bus)
-{
-	pci_devfn_t dev;
-
-	/* Find the device. */
-	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
-				       PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
-	return (dev >> 15) & 0x1f;
-}
-
-static void sio_setup(void)
-{
-	uint32_t dword;
-	uint8_t byte;
-	enable_smbus();
-//	smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */
-	smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
-
-	byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b);
-	byte |= 0x20;
-	pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0x7b, byte);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0);
-	dword |= (1 << 0);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa0, dword);
-
-	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4);
-	dword |= (1 << 16);
-	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1, 0), 0xa4, dword);
-}
-
-static const u8 spd_addr[] = {
-	/* first node */
-	RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
-	/* second node */
-	RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
-#endif
-#if CONFIG_MAX_PHYSICAL_CPUS > 2
-	/* third node */
-	RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
-	/* fourth node */
-	RC03, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
-#endif
-};
-
-#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
-#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
-#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
-
-static void write_GPIO(void)
-{
-	pnp_enter_conf_state(GPIO1_DEV);
-	pnp_set_logical_device(GPIO1_DEV);
-	pnp_write_config(GPIO1_DEV, 0x30, 0x01);
-	pnp_write_config(GPIO1_DEV, 0x60, 0x00);
-	pnp_write_config(GPIO1_DEV, 0x61, 0x00);
-	pnp_write_config(GPIO1_DEV, 0x62, 0x00);
-	pnp_write_config(GPIO1_DEV, 0x63, 0x00);
-	pnp_write_config(GPIO1_DEV, 0x70, 0x00);
-	pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
-	pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
-	pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
-	pnp_exit_conf_state(GPIO1_DEV);
-
-	pnp_enter_conf_state(GPIO2_DEV);
-	pnp_set_logical_device(GPIO2_DEV);
-	pnp_write_config(GPIO2_DEV, 0x30, 0x01);
-	pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
-	pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
-	pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
-	pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
-	pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
-	pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
-	pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
-	pnp_exit_conf_state(GPIO2_DEV);
-
-	pnp_enter_conf_state(GPIO3_DEV);
-	pnp_set_logical_device(GPIO3_DEV);
-	pnp_write_config(GPIO3_DEV, 0x30, 0x00);
-	pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
-	pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
-	pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
-	pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
-	pnp_exit_conf_state(GPIO3_DEV);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	struct sys_info *sysinfo = get_sysinfo();
-	u32 bsp_apicid = 0, val, wants_reset;
-	msr_t msr;
-
-	timestamp_init(timestamp_get());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		/* Nothing special needs to be done to find bus 0 */
-		/* Allow the HT devices to be found */
-		set_bsp_node_CHtExtNodeCfgEn();
-		enumerate_ht_chain();
-		sio_setup();
-	}
-
-	post_code(0x30);
-
-	if (bist == 0)
-		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
-	post_code(0x32);
-
-	winbond_set_clksel_48(SUPERIO_DEV);
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
-	console_init();
-	write_GPIO();
-	printk(BIOS_DEBUG, "\n");
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-	printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	/* Setup sysinfo defaults */
-	set_sysinfo_in_ram(0);
-
-	update_microcode(val);
-
-	post_code(0x33);
-
-	cpuSetAMDMSR(0);
-	post_code(0x34);
-
-	amd_ht_init(sysinfo);
-	post_code(0x35);
-
-	/* Setup nodes PCI space and start core 0 AP init. */
-	finalize_node_setup(sysinfo);
-
-	/* Setup any mainboard PCI settings etc. */
-	setup_mb_resource_map();
-	post_code(0x36);
-
-	/* wait for all the APs core0 started by finalize_node_setup. */
-	/* FIXME: A bunch of cores are going to start output to serial at once.
-	* It would be nice to fixup prink spinlocks for ROM XIP mode.
-	* I think it could be done by putting the spinlock flag in the cache
-	* of the BSP located right after sysinfo.
-	*/
-
-	wait_all_core0_started();
-#if CONFIG(LOGICAL_CPUS)
-	/* Core0 on each node is configured. Now setup any additional cores. */
-	printk(BIOS_DEBUG, "start_other_cores()\n");
-	start_other_cores(bsp_apicid);
-	post_code(0x37);
-	wait_all_other_cores_started(bsp_apicid);
-#endif
-
-	post_code(0x38);
-
-#if CONFIG(SET_FIDVID)
-	msr = rdmsr(MSR_COFVID_STS);
-	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-
-	/* FIXME: The sb fid change may survive the warm reset and only
-	* need to be done once.*/
-
-	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-	post_code(0x39);
-
-	if (!warm_reset_detect(0)) {      // BSP is node 0
-		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
-	} else {
-		init_fidvid_stage2(bsp_apicid, 0);  // BSP is node 0
-	}
-
-	post_code(0x3A);
-
-	/* show final fid and vid */
-	msr = rdmsr(MSR_COFVID_STS);
-	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-#endif
-
-	init_timer(); // Need to use TMICT to synchronize FID/VID
-
-	wants_reset = mcp55_early_setup_x();
-
-	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
-	if (!warm_reset_detect(0)) {
-		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
-		soft_reset();
-		die("After soft_reset - shouldn't see this message!!!\n");
-	}
-
-	if (wants_reset)
-		printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
-
-	post_code(0x3B);
-
-	/* It's the time to set ctrl in sysinfo now; */
-	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
-	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
-	post_code(0x3D);
-
-//	printk(BIOS_DEBUG, "enable_smbus()\n");
-//	enable_smbus(); /* enable in sio_setup */
-
-	post_code(0x40);
-
-	raminit_amdmct(sysinfo);
-
-	cbmem_initialize_empty();
-	post_code(0x41);
-
-	amdmct_cbmem_store_info(sysinfo);
-
-}
-
-/**
- * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
- * Description:
- *	This routine is called every time a non-coherent chain is processed.
- *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
- *	swap list. The first part of the list controls the BUID assignment and the
- *	second part of the list provides the device to device linking.  Device orientation
- *	can be detected automatically, or explicitly.  See documentation for more details.
- *
- *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- *	based on each device's unit count.
- *
- * Parameters:
- *	@param[in]  node   = The node on which this chain is located
- *	@param[in]  link   = The link on the host for this chain
- *	@param[out] List   = supply a pointer to a list
- */
-BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
-{
-	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
-	/* If the BUID was adjusted in early_ht we need to do the manual override */
-	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
-		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
-		if ((node == 0) && (link == 0)) {	/* BSP SB link */
-			*List = swaplist;
-			return 1;
-		}
-	}
-
-	return 0;
-}