Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 53 insertions, 53 deletions

diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout
index 9d37e2bba6..518f9458b6 100644
--- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout
+++ b/src/mainboard/supermicro/h8qme_fam10/cmos.layout
@@ -1,23 +1,23 @@
-## 
+##
 ## This file is part of the coreboot project.
-## 
+##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 entries
 
diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
index 51c2feb000..5759f40ccf 100644
--- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
+++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
@@ -8,9 +8,9 @@ chip northbridge/amd/amdfam10/root_complex
 		chip northbridge/amd/amdfam10 #mc0
 			device pci 18.0 on end
 			device pci 18.0 on end
-			device pci 18.0 on 
+			device pci 18.0 on
         # SB on link 2.0
-			        chip southbridge/nvidia/mcp55 
+			        chip southbridge/nvidia/mcp55
 					device pci 0.0 on end   # HT
                 			device pci 1.0 on # LPC
 						chip superio/winbond/w83627hf
@@ -37,14 +37,14 @@ chip northbridge/amd/amdfam10/root_complex
                 	                			irq 0x70 = 1
 								irq 0x72 = 12
 							end
-                	        			device pnp 2e.6 off  # SFI 
+                	        			device pnp 2e.6 off  # SFI
                 	                 			io 0x62 = 0x100
 							end
                 	        			device pnp 2e.7 off #  GPIO_GAME_MIDI
 								io 0x60 = 0x220
 								io 0x62 = 0x300
 								irq 0x70 = 9
-							end						
+							end
                 	        			device pnp 2e.8 off end #  WDTO_PLED
                 	        			device pnp 2e.9 off end #  GPIO_SUSLED
                 	        			device pnp 2e.a off end #  ACPI
@@ -57,12 +57,12 @@ chip northbridge/amd/amdfam10/root_complex
 					device pci 1.1 on end
                                         device pci 1.1 on # SM 1
 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#                                                         
+#
                                                 chip drivers/generic/generic #MAC EEPROM
                                                         device i2c 51 on end
-                                                end 
+                                                end
 
-                                        end # SM 
+                                        end # SM
 	                		device pci 2.0 on end # USB 1.1
         	        		device pci 2.1 on end # USB 2
                 			device pci 4.0 on end # IDE
@@ -70,7 +70,7 @@ chip northbridge/amd/amdfam10/root_complex
 	                		device pci 5.1 on end # SATA 1
 	                		device pci 5.2 on end # SATA 2
 					device pci 6.1 off end # AZA
-					device pci 7.0 on 
+					device pci 7.0 on
 					    device pci 1.0 on end
 					end
 					device pci 8.0 off end
@@ -87,7 +87,7 @@ chip northbridge/amd/amdfam10/root_complex
 					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" = "0x51"
 				end
-			end #  device pci 18.0 
+			end #  device pci 18.0
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
@@ -110,10 +110,10 @@ chip northbridge/amd/amdfam10/root_complex
 			device pci 19.3 on end
 			device pci 19.4 on end
 		end # mc0
-		
+
 	end # PCI domain
-	
-#       chip drivers/generic/debug 
+
+#       chip drivers/generic/debug
 #               device pnp 0.0 off end # chip name
 #                device pnp 0.1 on end # pci_regs_all
 #                device pnp 0.2 off end # mem
@@ -124,5 +124,5 @@ chip northbridge/amd/amdfam10/root_complex
 #                device pnp 0.7 off end # tsc
 #                device pnp 0.8 off  end # io
 #                device pnp 0.9 on end # io
-#       end  
+#       end
 end #root_complex
diff --git a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c
index efaf4cb754..9338d5e08c 100644
--- a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c
+++ b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c
@@ -19,7 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/* This file was generated by getpir.c, do not modify! 
+/* This file was generated by getpir.c, do not modify!
  * (but if you do, please run checkpir on it to verify)
  * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
 
@@ -34,11 +34,11 @@
 #include <cpu/amd/amdfam10_sysconf.h>
 #include "mb_sysconf.h"
 
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
 		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
 		uint8_t slot, uint8_t rfu)
 {
-	pirq_info->bus = bus; 
+	pirq_info->bus = bus;
 	pirq_info->devfn = devfn;
 		pirq_info->irq[0].link = link0;
 		pirq_info->irq[0].bitmap = bitmap0;
@@ -80,15 +80,15 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
-	
+
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version  = PIRQ_VERSION;
-	
+
 	pirq->rtr_bus = m->bus_mcp55[0];
 	pirq->rtr_devfn = ((sbdn+6)<<3)|0;
 
 	pirq->exclusive_irqs = 0;
-	
+
 	pirq->rtr_vendor = 0x10de;
 	pirq->rtr_device = 0x0364;
 
@@ -101,7 +101,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 //pci bridge
 	write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0);
 	pirq_info++; slot_num++;
-	
+
 	for(i=1; i< sysconf.hc_possible_num; i++) {
 		if(!(sysconf.pci1234[i] & 0x1) ) continue;
 		unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
@@ -120,10 +120,10 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	}
 #endif
 
-	pirq->size = 32 + 16 * slot_num; 
+	pirq->size = 32 + 16 * slot_num;
 
 	for (i = 0; i < pirq->size; i++)
-		sum += v[i];	
+		sum += v[i];
 
 	sum = pirq->checksum - sum;
 
diff --git a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
index 42969bb71e..5a17fa9442 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
+++ b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
@@ -26,7 +26,7 @@ struct mb_sysconf_t {
 	unsigned char bus_isa;
 	unsigned char bus_mcp55[8]; //1
 	unsigned apicid_mcp55;
-	unsigned bus_type[256]; 
+	unsigned bus_type[256];
 
 	unsigned char bus_8132_0;  //7
 	unsigned char bus_8132_1;  //8
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index 551ee977fa..c365ddbe2d 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -100,33 +100,33 @@ static void *smp_write_config_table(void *v)
 
 
 	}
-		
+
 		   /*I/O Ints:	Type	Polarity    Trigger			Bus ID	 IRQ	APIC ID	PIN# */
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_mcp55, 0x1); 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_mcp55, 0x2); 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x3, m->apicid_mcp55, 0x3); 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x4, m->apicid_mcp55, 0x4); 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x6, m->apicid_mcp55, 0x6); 
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
-	
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5);  /*  5 SMBus, OK */ 
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5);  /*  5 SMBus, OK */
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x5); /*  5  IDE, OK*/
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ 
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ 
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/
-	
+
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5  eth0, OK*/
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
 
-	for(j=7;j>=2; j--) { 
+	for(j=7;j>=2; j--) {
 		if(!m->bus_mcp55[j]) continue;
 		for(i=0;i<4;i++) {
 			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
index 13ae166708..0aded2ccbd 100644
--- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
+++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
@@ -161,7 +161,7 @@ static void setup_mb_resource_map(void)
 		 *	   1 = base/limit registers i are read-only
 		 * [ 7: 4] Reserved
 		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
@@ -218,7 +218,7 @@ static void setup_mb_resource_map(void)
 		 * [ 3: 2] Reserved
 		 * [ 4: 4] VGA Enable
 		 *	   0 = VGA matches Disabled
-		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
 		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 		 * [ 5: 5] ISA Enable
 		 *	   0 = ISA matches Disabled
@@ -226,7 +226,7 @@ static void setup_mb_resource_map(void)
 		 *	       from matching agains this base/limit pair
 		 * [11: 6] Reserved
 		 * [24:12] PCI I/O Base i
-		 *	   This field defines the start of PCI I/O region n 
+		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
 		// WARD CHANGED
@@ -273,9 +273,9 @@ static void setup_mb_resource_map(void)
 		 */
 		// WARD CHANGED
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
 
 	};
 
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index aa2081f7df..0d1657a170 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -93,12 +93,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 
-#include "resourcemap.c" 
+#include "resourcemap.c"
 
 #include "cpu/amd/quadcore/quadcore.c"
 
 #define MCP55_NUM 1
-#define MCP55_USE_NIC 0 
+#define MCP55_USE_NIC 0
 #define MCP55_USE_AZA 0
 
 #define MCP55_PCI_E_X_0 4
@@ -128,13 +128,13 @@ static void sio_setup(void)
 	smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 
         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
+        byte |= 0x20;
         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-        
+
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
         dword |= (1<<0);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-        
+
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
         dword |= (1<<16);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
@@ -206,7 +206,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         }
 
   post_code(0x30);
- 
+
         if (bist == 0) {
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }