diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-19 09:47:16 -0600 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-20 21:55:12 +0200 |
commit | a5aad2ed68690d748c650f69a2e39f91a7b02608 (patch) | |
tree | 7ad419bc13bcf13e546481558aa1a4c923821c07 /src/mainboard/supermicro/h8dmr_fam10 | |
parent | 531b87ac4e8038aedf9c44c29fe2c1fc31adb346 (diff) |
src/mainboard/lenovo-winent: Add space around operators
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/supermicro/h8dmr_fam10')
-rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c | 6 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/mptable.c | 10 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 |
3 files changed, 9 insertions, 9 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index 673910562e..8a0a6ec51f 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) device_t dev; int i; - if(get_bus_conf_done==1) return; //do it only once + if(get_bus_conf_done == 1) return; //do it only once get_bus_conf_done = 1; @@ -79,7 +79,7 @@ void get_bus_conf(void) memset(m, 0, sizeof(struct mb_sysconf_t)); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { + for(i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; } @@ -98,7 +98,7 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); } - for(i=2; i<8;i++) { + for(i = 2; i < 8; i++) { dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); if (dev) { m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index e1ca607888..631ff7d488 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -88,15 +88,15 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 - for(j=7; j>=2; j--) { + for(j = 7; j >= 2; j--) { if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + for(i = 0; i < 4; i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00 << 2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } - for(j=0; j<1; j++) - for(i=0;i<4;i++) { + for(j = 0; j < 1; j++) + for(i = 0; i < 4; i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 7be3209ecb..7766f3a5bf 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -71,7 +71,7 @@ static void sio_setup(void) uint8_t byte; enable_smbus(); - // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ + // smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */ /* set FAN ctrl to DC mode */ smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); |