Remove failover/fallback/normal handling in mainboards'

romstage.c. That's newconfig stuff.

1. In failover_process(), I removed the fallback/normal selection logic
and kept the remaining hardware init in. The if-clauses' conditions are
reverted to match.
Remove #if failover||fallback guard.

2. Change cache_as_ram_main() to first call failover_process, then
real_main unconditionally.

3. Move failover_process's code to the beginning of real_main, remove
failover_process and its call in cache_as_ram_main.

4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same
arguments, so no problem with that)


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 14 insertions, 72 deletions

diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 9d870f0c8d..0aa934b3ca 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -135,8 +135,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #endif
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -165,81 +163,12 @@ static void sio_setup(void)
 
 }
 
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-        unsigned last_boot_normal_x = last_boot_normal();
-
-        /* Is this a cpu only reset? or Is this a secondary cpu? */
-        if ((cpu_init_detectedx) || (!boot_cpu())) {
-                if (last_boot_normal_x) {
-                        goto normal_image;
-                } else {
-                        goto fallback_image;
-                }
-        }
-
-        /* Nothing special needs to be done to find bus 0 */
-        /* Allow the HT devices to be found */
-
-        set_bsp_node_CHtExtNodeCfgEn();
-        enumerate_ht_chain();
-
-        sio_setup();
-
-        /* Setup the mcp55 */
-        mcp55_enable_rom();
-
-        /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal_x) {
-                goto normal_image;
-        }
-        /* This is the primary cpu how should I boot? */
-        else if (do_normal_boot()) {
-                goto normal_image;
-        }
-        else {
-                goto fallback_image;
-        }
- normal_image:
-        __asm__ volatile ("jmp __normal_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                );
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
-        __asm__ volatile ("jmp __fallback_image"
-                : /* outputs */
-                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
-                )
-#endif
-	;
-}
-#endif
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-#if CONFIG_HAVE_FAILOVER_BOOT==1 
-    #if CONFIG_USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);	
-    #else
-	real_main(bist, cpu_init_detectedx);
-    #endif
-#else
-    #if CONFIG_USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);	
-    #endif
-	real_main(bist, cpu_init_detectedx);
-#endif
-}
-
 #if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
   struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
@@ -248,6 +177,19 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 wants_reset;
 	msr_t msr;
 
+        if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+
+		sio_setup();
+
+		/* Setup the mcp55 */
+		mcp55_enable_rom();
+        }
+
   post_code(0x30);
  
         if (bist == 0) {