diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-01-06 09:14:08 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-01-06 09:14:08 +0000 |
| commit | 753169dc251e3f5e71a9f678c93b68c040aebbf0 (patch) | |
| tree | ceeb73865d95baead8572ac423ed633f2d5c5495 /src/mainboard/supermicro/h8dmr_fam10/Kconfig | |
| parent | 95c50c6091cdc700c79da832f61b2a94b3e5c87c (diff) | |
Kconfig builds all boards now.
This patch also aligns the configuration of a couple of
boards more closely to what newconfig does.
Also, the romstrap inc/lds files are declared in the
Makefiles of the southbridges they belong to, instead of
some global file.
AMD CPUs have their own timer functions, so disable UDELAY_IO
for them and set HAVE_INIT_TIMER as appropriate, same for
emulation/qemu-x86.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro/h8dmr_fam10/Kconfig')
| -rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/Kconfig | 38 |
1 files changed, 30 insertions, 8 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index edface050b..fdae17e44b 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -15,6 +15,8 @@ config BOARD_SUPERMICRO_H8DMR_FAM10 select LIFT_BSP_APIC_ID select AMDMCT select BOARD_ROMSIZE_KB_1024 + select TINY_BOOTBLOCK + select ENABLE_APIC_EXT_ID config MAINBOARD_DIR string @@ -23,27 +25,42 @@ config MAINBOARD_DIR config DCACHE_RAM_BASE hex - default 0xc8000 + default 0xc4000 depends on BOARD_SUPERMICRO_H8DMR_FAM10 config DCACHE_RAM_SIZE hex - default 0x08000 + default 0x0c000 depends on BOARD_SUPERMICRO_H8DMR_FAM10 config DCACHE_RAM_GLOBAL_VAR_SIZE hex - default 0x01000 + default 0x04000 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config RAMBASE + hex + default 0x200000 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config RAMTOP + hex + default 0x1000000 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config HEAP_SIZE + hex + default 0xc0000 depends on BOARD_SUPERMICRO_H8DMR_FAM10 config APIC_ID_OFFSET hex - default 0x10 + default 0x0 depends on BOARD_SUPERMICRO_H8DMR_FAM10 config MEM_TRAIN_SEQ int - default 1 + default 2 depends on BOARD_SUPERMICRO_H8DMR_FAM10 config SB_HT_CHAIN_ON_BUS0 @@ -78,7 +95,7 @@ config HW_MEM_HOLE_SIZEK config MAX_CPUS int - default 4 + default 8 depends on BOARD_SUPERMICRO_H8DMR_FAM10 config MAX_PHYSICAL_CPUS @@ -88,12 +105,12 @@ config MAX_PHYSICAL_CPUS config HT_CHAIN_END_UNITID_BASE hex - default 0x0 + default 0x20 depends on BOARD_SUPERMICRO_H8DMR_FAM10 config HT_CHAIN_UNITID_BASE hex - default 0x0 + default 0x1 depends on BOARD_SUPERMICRO_H8DMR_FAM10 config USE_INIT @@ -115,3 +132,8 @@ config AMD_UCODE_PATCH_FILE string default "mc_patch_0100009f.h" depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_SUPERMICRO_H8DMR_FAM10 |