diff options
| author | Damien Zammit <damien@zamaudio.com> | 2016-11-28 00:29:10 +1100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-04 18:56:01 +0100 |
| commit | 75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7 (patch) | |
| tree | 618c2bc04f44cf73d3dae288bff0a5e2ef44d616 /src/mainboard/sunw | |
| parent | 6c20b65849aeda664cc40ebc0f0bab2e99768423 (diff) | |
amdfam10: Perform major include ".c" cleanup
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Diffstat (limited to 'src/mainboard/sunw')
| -rw-r--r-- | src/mainboard/sunw/ultra40m2/romstage.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index a7489daa6b..51f5a85138 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -36,10 +36,22 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1) +unsigned get_sbdn(unsigned bus); + +unsigned get_sbdn(unsigned bus) +{ + pci_devfn_t dev; + + /* Find the device. */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + + return (dev >> 15) & 0x1f; +} + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -48,6 +60,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" |