mainboard: copy nvidia/l1_2pvv to sunw/ultra40m2 and rename

Change-Id: Ia275a697caa73168553b5d588d54df651e0539d7
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/12303
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 75 insertions, 0 deletions

diff --git a/src/mainboard/sunw/ultra40m2/Kconfig b/src/mainboard/sunw/ultra40m2/Kconfig
new file mode 100644
index 0000000000..5b19c13568
--- /dev/null
+++ b/src/mainboard/sunw/ultra40m2/Kconfig
@@ -0,0 +1,75 @@
+if BOARD_SUNW_ULTRA40M2
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select CPU_AMD_SOCKET_F
+	select DIMM_DDR2
+	select DIMM_REGISTERED
+	select NORTHBRIDGE_AMD_AMDK8
+	select SOUTHBRIDGE_NVIDIA_MCP55
+	select HT_CHAIN_DISTRIBUTE
+	select MCP55_USE_NIC
+	select MCP55_USE_AZA
+	select SUPERIO_WINBOND_W83627EHG
+	select PARALLEL_CPU_INIT
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select LIFT_BSP_APIC_ID
+	select BOARD_ROMSIZE_KB_512
+	select QRANK_DIMM_SUPPORT
+	select K8_ALLOCATE_IO_RANGE
+
+config MAINBOARD_DIR
+	string
+	default sunw/ultra40m2
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x08000
+
+config APIC_ID_OFFSET
+	hex
+	default 0x10
+
+config MEM_TRAIN_SEQ
+	int
+	default 1
+
+config MCP55_NUM
+	int
+	default 2
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Ultra 40 M2"
+
+config MAX_CPUS
+	int
+	default 4
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x20
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+
+config MCP55_PCI_E_X_0
+	int
+	default 2
+
+endif # BOARD_SUNW_ULTRA40M2