diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2024-09-09 12:56:31 +0100 |
|---|---|---|
| committer | Sean Rhodes <sean@starlabs.systems> | 2024-10-03 09:35:01 +0000 |
| commit | 2e1aa62839038339cdeee174d2fb2711fe5d9152 (patch) | |
| tree | ef904dfca6b38abb2c3ae82daa81f83062c9dc1b /src/mainboard/starlabs | |
| parent | 05530b704a2b638cfee60c9fe65efacdef46a65f (diff) | |
mb/starlabs/starbook/kbl: Alphabetize and group FSP UPDs
Change-Id: I5beda22208fe17338d4136f9d38fd50e55054b01
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/starlabs')
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index 87ccb8a035..bc8bc62c23 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake -# CPU - # Enable Enhanced Intel SpeedStep + # FPD UPDs register "eist_enable" = "true" + register "SaGv" = "SaGv_Enabled" # Graphics # IGD Displays @@ -14,10 +14,6 @@ chip soc/intel/skylake .backlight_pwm_hz = 200, // PWM }" - # FSP Memory - register "SaGv" = "SaGv_Enabled" - -# FSP Silicon # Serial I/O register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, |