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authorSean Rhodes <sean@starlabs.systems>2024-09-09 12:56:49 +0100
committerSean Rhodes <sean@starlabs.systems>2024-10-03 09:35:06 +0000
commit26b3847269eb93b91aece284fc1de430f272504c (patch)
treeda5f008cf94de6899f14f0b4f1f65afb5ff05bcf /src/mainboard/starlabs/starbook/variants
parent2e1aa62839038339cdeee174d2fb2711fe5d9152 (diff)
mb/starlabs/starbook/kbl: Remove PMC GPIO routing
Change-Id: Ibb92d76f15be71ecb1e2187c7e235235585f8793 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/starlabs/starbook/variants')
-rw-r--r--src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
index bc8bc62c23..438fbcfc0e 100644
--- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
@@ -26,16 +26,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "3" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
- # PM Util
- # GPE configuration
- # Note that GPE events called out in ASL code rely on this
- # route. i.e. If this route changes then the affected GPE
- # offset bits also need to be changed.
- # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
- register "gpe0_dw0" = "GPP_B"
- register "gpe0_dw1" = "GPP_C"
- register "gpe0_dw2" = "GPP_E"
-
# Enable the correct decode ranges on the LPC bus.
register "lpc_ioe" = "LPC_IOE_EC_4E_4F |
LPC_IOE_KBC_60_64 |