diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2024-09-09 12:38:18 +0100 |
|---|---|---|
| committer | Sean Rhodes <sean@starlabs.systems> | 2024-10-03 09:34:14 +0000 |
| commit | 21443bccdab212a060a58bdfc993423f49f84fc6 (patch) | |
| tree | 755023e0d015f581d0fcccd2baf6335f9c830462 /src/mainboard/starlabs/starbook/variants/cml | |
| parent | 55de4d9ab4deeccd39f8c970e6b32a1e19bff28b (diff) | |
mb/starlabs/starbook/cml: Remove PMC GPIO routing
These aren't used so remove them.
Change-Id: I6b9cf29843047bff9a37f82b899ff1d10b206888
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/mainboard/starlabs/starbook/variants/cml')
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/cml/devicetree.cb | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index 0070f22374..d9858401cf 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -28,16 +28,6 @@ chip soc/intel/cannonlake register "PchPmSlpSusMinAssert" = "3" # 500ms register "PchPmSlpAMinAssert" = "3" # 2s - # PM Util - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) - register "gpe0_dw0" = "PMC_GPP_B" - register "gpe0_dw1" = "PMC_GPP_C" - register "gpe0_dw2" = "PMC_GPP_E" - # PCIe Clock register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" |