diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2022-06-16 22:42:31 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-20 12:10:42 +0000 |
| commit | 8a1eb1993d9e48305a82b670c34bafefa9730594 (patch) | |
| tree | c3856cc1e8db83e4316beeff1b8b0f87ecfbad6c /src/mainboard/starlabs/lite/variants/glkr/devicetree.cb | |
| parent | 8a4f0768948a7f32aeb7dee495e7c85e650597fd (diff) | |
mb/starlabs/lite/glkr: Correct USB port numbers
The USB ports for the Motherboard USB 3.0 and Type-C were labelled
incorrectly. This change swaps the ports, so they are labelled correctly
and also corrects the over-current pins that they use.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I80484dc8bdd68dd72b3848720c790d59237a9f8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/starlabs/lite/variants/glkr/devicetree.cb')
| -rw-r--r-- | src/mainboard/starlabs/lite/variants/glkr/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 1b4ddce3b4..057fc2b51a 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -89,11 +89,11 @@ chip soc/intel/apollolake ### USB 2.0 Devices # Motherboard USB Type C register "usb2_port[0]" = "PORT_EN(OC1)" - register "usb3_port[1]" = "PORT_EN(OC1)" + register "usb3_port[0]" = "PORT_EN(OC1)" # Motherboard USB 3.0 register "usb2_port[1]" = "PORT_EN(OC0)" - register "usb3_port[0]" = "PORT_EN(OC0)" + register "usb3_port[1]" = "PORT_EN(OC0)" # Daughterboard USB 3.0 register "usb2_port[3]" = "PORT_EN(OC1)" |