src/mainboard: Add Star Labs labtop series

Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

2 files changed, 380 insertions, 0 deletions

diff --git a/src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h b/src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h
new file mode 100644
index 0000000000..a20be3122b
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/include/variant/gpio.h
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _VARIANT_GPIO_H_
+#define _VARIANT_GPIO_H_
+
+#include "baseboard/variants.h"
+
+#ifndef __ACPI__
+
+/*
+ * All definitions are taken from a comparison of the output of "inteltool -a"
+ * using the stock BIOS and with coreboot.
+ */
+
+/* Early pad configuration in romstage.c */
+const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPO(GPP_E22, 1, PLTRST),
+	PAD_CFG_GPO(GPP_E23, 1, PLTRST),
+	PAD_CFG_GPI(GPP_H6, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_H7, NONE, PLTRST),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Pad configuration in ramstage.c */
+const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD7, 0, PWROK),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_A7, 0x40100100, 0x3000),
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A15, 1, PLTRST),
+	PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST),
+	PAD_NC(GPP_A17, NONE),
+	PAD_NC(GPP_A18, UP_20K),
+	PAD_NC(GPP_A19, UP_20K),
+	PAD_NC(GPP_A20, UP_20K),
+	PAD_NC(GPP_A21, UP_20K),
+	PAD_NC(GPP_A22, UP_20K),
+	PAD_NC(GPP_A23, UP_20K),
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0000),
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B11, 1, PLTRST),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
+	PAD_CFG_TERM_GPO(GPP_B15, 1, UP_20K, PLTRST),
+	_PAD_CFG_STRUCT(GPP_B16, 0x80100100, 0x0000),
+	PAD_CFG_GPO(GPP_B17, 1, PLTRST),
+	PAD_CFG_GPO(GPP_B18, 0, DEEP),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	PAD_CFG_GPO(GPP_B23, 1, DEEP),
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C2, 1, DEEP),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_C5, 0x40880100, 0x0000),
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
+	_PAD_CFG_STRUCT(GPP_C8, 0x80100100, 0x3000),
+	_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000),
+	PAD_CFG_GPO(GPP_C10, 0, PLTRST),
+	_PAD_CFG_STRUCT(GPP_C11, 0x40100100, 0x0000),
+	PAD_CFG_GPO(GPP_C12, 1, PLTRST),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_CFG_GPO(GPP_C15, 1, PLTRST),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_GPO(GPP_D9, 1, PLTRST),
+	_PAD_CFG_STRUCT(GPP_D10, 0x80100100, 0x0000),
+	_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000),
+	PAD_CFG_GPO(GPP_D12, 0, DEEP),
+	PAD_NC(GPP_D13, NONE),
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D15, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D16, 0, PWROK),
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+	PAD_NC(GPP_D21, NONE),
+	PAD_NC(GPP_D22, NONE),
+	PAD_NC(GPP_D23, NONE),
+	PAD_NC(GPP_E0, NONE),
+	PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
+	PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST),
+	_PAD_CFG_STRUCT(GPP_E3, 0x82040100, 0x0000),
+	_PAD_CFG_STRUCT(GPP_E4, 0x80880100, 0x3000),
+	PAD_NC(GPP_E5, NONE),
+	PAD_NC(GPP_E6, NONE),
+	PAD_CFG_GPI(GPP_E7, NONE, PLTRST),
+	PAD_NC(GPP_E8, NONE),
+	_PAD_CFG_STRUCT(GPP_E9, 0x44001700, 0x0000),
+	_PAD_CFG_STRUCT(GPP_E10, 0x44001700, 0x0000),
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E15, 1, PLTRST),
+	_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x3000),
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_F0, 0x00000301, 0x0000),
+	PAD_CFG_GPO(GPP_F1, 0, PWROK),
+	PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST),
+	_PAD_CFG_STRUCT(GPP_F3, 0x84000300, 0x3000),
+	PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_F8, NONE),
+	PAD_NC(GPP_F9, NONE),
+	PAD_CFG_GPI(GPP_F10, UP_20K, PLTRST),
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1),
+	PAD_NC(GPP_G0, NONE),
+	PAD_NC(GPP_G1, NONE),
+	PAD_NC(GPP_G2, NONE),
+	PAD_NC(GPP_G3, NONE),
+	PAD_NC(GPP_G4, NONE),
+	PAD_NC(GPP_G5, UP_20K),
+	PAD_NC(GPP_G6, NONE),
+	PAD_NC(GPP_G7, DN_20K),
+	PAD_NC(GPP_H0, UP_20K),
+	PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3),
+	PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3),
+	PAD_NC(GPP_H3, UP_20K),
+	PAD_NC(GPP_H4, NONE),
+	PAD_NC(GPP_H5, NONE),
+	PAD_NC(GPP_H8, NONE),
+	PAD_NC(GPP_H9, NONE),
+	PAD_CFG_GPO(GPP_H10, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H11, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H12, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H13, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H14, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H15, 1, PLTRST),
+	PAD_NC(GPP_H16, NONE),
+	PAD_CFG_GPO(GPP_H17, 0, DEEP),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_H19, 1, PLTRST),
+	_PAD_CFG_STRUCT(GPP_H20, 0x84000300, 0x0000),
+	PAD_CFG_GPO(GPP_H21, 0, DEEP),
+	PAD_CFG_GPO(GPP_H22, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H23, 0, DEEP),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+#endif
+
+#endif
diff --git a/src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h b/src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h
new file mode 100644
index 0000000000..190474f6d1
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/cml/include/variant/hda_verb.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _HDA_VERB_H_
+#define _HDA_VERB_H_
+
+#include <device/azalia_device.h>
+#include <device/azalia.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256,	// Codec Vendor / Device ID: Realtek ALC256
+	0xffffffff,	// Subsystem ID
+	0x0000002b,	// Number of jacks (NID entries)
+
+	/* Rest Codec First */
+	AZALIA_RESET(0x1),
+
+	/* HDA Codec Subsystem ID Verb-table
+	 HDA Codec Subsystem ID: 0x10EC119E */
+	0x0017209E,
+	0x00172111,
+	0x001722EC,
+	0x00172310,
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90171110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x02ab1020),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x022b1010),
+	/* ONE DOES NOT SIMPLY
+	   MAKE IT WORK WITH WINDOWS */
+	/* RESET to D0 */
+	0x00170500,
+	0x00170500,
+	0x00170500,
+	0x00170500,
+	/* RESET Register */
+	0x0205001A,
+	0x02048003,
+	0x0205001A,
+	0x0204C003,
+	/* ALC256 default-1(Class D RESET) */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+	/* ALC256 default-2 */
+	0x02050040,
+	0x02049800,
+	0x02050034,
+	0x0204023C,
+	/* ALC256 Speaker output power - 4 ohm 2.2W (+12dB gain) + Combo Jack TRS setting */
+	0x02050038,
+	0x02047901,
+	0x02050045,
+	0x02045089,
+	/* H/W AGC setting-1 */
+	0x02050016,
+	0x02040C50,
+	0x02050012,
+	0x0204EBC2,
+	/* H/W AGC setting-2 */
+	0x02050013,
+	0x0204401D,
+	0x02050016,
+	0x02044E50,
+	/* Zero data  + EAPD to verb-control */
+	0x02050037,
+	0x0204FE15,
+	0x02050010,
+	0x02040020,
+	/* Zero data */
+	0x02050030,
+	0x02048000,
+	0x02050030,
+	0x02048000,
+	/* ALC256 default-3 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+	/* ALC256 default-4 */
+	0x0205001B,
+	0x02040A4B,
+	0x02050008,
+	0x02046A6C,
+	/* JD1 */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+	/* Microphone + Array MIC  security Disable  +ADC clock Enable */
+	0x0205000D,
+	0x0204A020,
+	0x02050005,
+	0x02040700,
+	/* Speaker Enable */
+	0x0205000C,
+	0x020401EF,
+	0x0205000C,
+	0x020401EF,
+	/* EQ Bypass + EQ HPF cutoff 250Hz */
+	0x05350000,
+	0x0534201A,
+	0x0535001d,
+	0x05340800,
+	/* EQ-2 */
+	0x0535001e,
+	0x05340800,
+	0x05350003,
+	0x05341EF8,
+	/* EQ-3 */
+	0x05350004,
+	0x05340000,
+	0x05450000,
+	0x05442000,
+	/* EQ-4 */
+	0x0545001d,
+	0x05440800,
+	0x0545001e,
+	0x05440800,
+	/* EQ-5 */
+	0x05450003,
+	0x05441EF8,
+	0x05450004,
+	0x05440000,
+	/* EQ Update */
+	0x05350000,
+	0x0534E01A,
+	0x05350000,
+	0x0534E01A,
+
+	0x8086280b, /* Codec Vendor / Device ID: Intel */
+	0x80860101, /* Subsystem ID */
+	0x00000004, /* Number of 4 dword sets */
+
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {
+};
+
+AZALIA_ARRAY_SIZES;
+
+#endif