diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2022-05-26 21:04:10 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-20 12:15:52 +0000 |
| commit | 99d2d62fa1034ac3935dd701735704ca839c25a1 (patch) | |
| tree | ce474cfbee6ee23701272da589fd4dee87c369e0 /src/mainboard/starlabs/labtop/variants/cml/devicetree.cb | |
| parent | 49d0204c31a50c5b470d5c65781790b378c5f903 (diff) | |
mb/starlabs/labtop: Configure tcc_offset based on power_profile settings
Set tcc_offset value based on the power_profile value, ranging from 10
to 20 degrees.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I66fb266c1730833ff6e2dbf8ea39f23ee0878590
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/starlabs/labtop/variants/cml/devicetree.cb')
| -rw-r--r-- | src/mainboard/starlabs/labtop/variants/cml/devicetree.cb | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb index 3bf0d7a74b..74125488f8 100644 --- a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb @@ -32,9 +32,6 @@ chip soc/intel/cannonlake register "PchPmSlpSusMinAssert" = "3" # 500ms register "PchPmSlpAMinAssert" = "3" # 2s - # Thermal - register "tcc_offset" = "10" - # PM Util # GPE configuration # Note that GPE events called out in ASL code rely on this |