diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2024-10-03 11:12:54 +0100 |
|---|---|---|
| committer | Sean Rhodes <sean@starlabs.systems> | 2024-10-11 11:27:18 +0000 |
| commit | 68f33d228ef2a79878042b7d62db63f73fa77561 (patch) | |
| tree | f9572ffb2a2002b363a6d667cdf9dcce11f4a025 /src/mainboard/starlabs/byte_adl/variants | |
| parent | 29b5f1ddcb164bff639ffb631095ab26013284d7 (diff) | |
mb/starlabs/*: Enhance USB configuration and comments
Some boards use hubs for devices, so correct the ACPI configuration
for these ports. Also, add more information to the comments for the
ports.
Change-Id: I8472130aba8e777557cf68280fa0058dbeb77df9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/mainboard/starlabs/byte_adl/variants')
| -rw-r--r-- | src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index 1d08df282d..efc1a9ced9 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -39,23 +39,23 @@ chip soc/intel/alderlake end device ref gna on end device ref xhci on - # Front panel USB Type C + # Front USB 3.0 Type-C register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" - # Back Top USB Type A [5] + # Back Top USB 3.0 Type-A register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" - # Back Bottom USB Type A [6] + # Back Bottom USB 3.0 Type-A register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" - # Front Left USB Type A [3] + # Front Left USB 3.0 Type-A register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" - # Front Right USB Type A [2] + # Front Right USB 3.0 Type-A register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" |