diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-02-24 11:01:54 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-10 16:55:35 +0100 |
| commit | 3d840d09aea6246347afea8f19dc1d71da06aba2 (patch) | |
| tree | 3490bd8e16a21f4b5e97edbe28e514573cf2c476 /src/mainboard/soyo | |
| parent | 422bf6b47226d68005003c17753fd30685e244c6 (diff) | |
northbridge/intel/i440bx: Unify UDELAY selection
Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i440BX boards in the chipset.
Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13781
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/soyo')
| -rw-r--r-- | src/mainboard/soyo/sy-6ba-plus-iii/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig b/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig index d09a6eab2b..1b5931ad22 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig +++ b/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F select HAVE_PIRQ_TABLE - select UDELAY_TSC select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index 9a8f0f8fda..1e25602d93 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> |