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authorUwe Poeche <uwe.poeche@siemens.com>2022-03-28 12:39:01 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-05-18 11:14:09 +0000
commit539fd2ac5a0f510d8434d4cc8a597f092325b8c8 (patch)
tree26b7b42ba97288d14ff218c4b49d2fc741a22d21 /src/mainboard/siemens
parentdb9873b69c52cc1eac5bfef72228f071e303a78f (diff)
intel/common/block: Provide RAPL and min clock ratio switches in common
There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens')
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig2
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig2
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig2
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig2
-rw-r--r--src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig2
5 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig
index ae76f7b7a2..052a58e623 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig
@@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
select RX6110SA_DISABLE_ACPI
select DRIVER_SIEMENS_NC_FPGA
select NC_FPGA_NOTIFY_CB_READY
- select APL_SKIP_SET_POWER_LIMITS
+ select SOC_INTEL_DISABLE_POWER_LIMITS
select DRIVERS_I2C_PTN3460
endif # BOARD_SIEMENS_MC_APL1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig
index d690157e85..306438d8fe 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig
@@ -8,6 +8,6 @@ config BOARD_SPECIFIC_OPTIONS
select RX6110SA_DISABLE_ACPI
select DRIVER_SIEMENS_NC_FPGA
select NC_FPGA_NOTIFY_CB_READY
- select APL_SKIP_SET_POWER_LIMITS
+ select SOC_INTEL_DISABLE_POWER_LIMITS
endif # BOARD_SIEMENS_MC_APL3
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig
index 5d3938b97d..6f600c70be 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig
@@ -4,7 +4,7 @@ if BOARD_SIEMENS_MC_APL4
config BOARD_SPECIFIC_OPTIONS
def_bool y
select DRIVER_INTEL_I210
- select APL_SET_MIN_CLOCK_RATIO
+ select SOC_INTEL_SET_MIN_CLOCK_RATIO
select MAINBOARD_HAS_TPM2
select MEMORY_MAPPED_TPM
select TPM_ON_FAST_SPI
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig
index a012ae24ae..7ab62fa1a0 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig
@@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
select RX6110SA_DISABLE_ACPI
select DRIVER_SIEMENS_NC_FPGA
select NC_FPGA_NOTIFY_CB_READY
- select APL_SKIP_SET_POWER_LIMITS
+ select SOC_INTEL_DISABLE_POWER_LIMITS
select MAINBOARD_HAS_TPM2
select MEMORY_MAPPED_TPM
select TPM_ON_FAST_SPI
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig
index bfbe1dd414..146e030dfc 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig
@@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
select RX6110SA_DISABLE_ACPI
select DRIVER_SIEMENS_NC_FPGA
select NC_FPGA_NOTIFY_CB_READY
- select APL_SKIP_SET_POWER_LIMITS
+ select SOC_INTEL_DISABLE_POWER_LIMITS
select MAINBOARD_HAS_TPM2
select MEMORY_MAPPED_TPM
select TPM_ON_FAST_SPI