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authorAaron Durbin <adurbin@chromium.org>2013-03-27 21:13:02 -0500
committerRonald G. Minnich <rminnich@gmail.com>2013-04-01 23:25:20 +0200
commitd6d6db3717d09f2b6a4590eec6016ca7d417c2f9 (patch)
tree851710c38debc2e4ea2e93fe6d16b145dfe7cff1 /src/mainboard/siemens/sitemp_g1p1/fadt.c
parentbab0a0b577ba8cc28aa1e2b2e9ec65fb98edced1 (diff)
lynxpoint: fix enable_pm1() function
The new enable_pm1() function was doing 2 things wrong: 1. It was doing a RMW of the pm1 register. This means we were keeping around the enables from the OS during S3 resume. This is bad in the face of the RTC alarm waking us up because it would cause an infinite stream of SMIs. 2. The register size of PM1_EN is 16-bits. However, the previous implementation was accessing it as a 32-bit register. The PM1 enables should only be set to what we expect to handle in the firmware before the OS changes to ACPI mode. Change-Id: Ib1d3caf6c84a1670d9456ed159420c6cb64f555e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2978 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/siemens/sitemp_g1p1/fadt.c')
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