diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2021-11-04 10:19:41 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-15 11:12:22 +0000 |
| commit | ed784bc0a79ce1c296a2685f22cb269d510403dd (patch) | |
| tree | a6ad1b2055fbf9768eedd659891aba27db3214ab /src/mainboard/siemens/mc_ehl | |
| parent | 3b037989537bd45350a41c5ae523f51aa44b492f (diff) | |
mb/siemens/mc_ehl: Disable HECI #2 device
HECI #2 is not used for CSE communication. Therefore, it is not
necessary to set the parameter 'Heci2Enable' in devicetree.
Change-Id: I7012e4d877a464699727ca775af3f9965e0602e9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_ehl')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index e96e654f8f..228bf60128 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -18,7 +18,6 @@ chip soc/intel/elkhartlake # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" - register "Heci2Enable" = "1" # Enable IBECC for the complete memory register "ibecc" = "{ diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 67ff3d0377..39789be85a 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -18,7 +18,6 @@ chip soc/intel/elkhartlake # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" - register "Heci2Enable" = "1" # Enable IBECC for the complete memory register "ibecc" = "{ |