mb/siemens/mc_ehl5: Add new board variant based on mc_ehl2

This mainboard is based on mc_ehl2. In a first step, it contains a copy
of mc_ehl2 directory with minimum changes. Special adaptations for
mc_ehl5 mainboard will follow in separate commits.

Change-Id: Id80f8eb49dd2fed0ed1ffc479d47d8669eca84c9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

6 files changed, 558 insertions, 0 deletions

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig
new file mode 100644
index 0000000000..1ad4ede557
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Kconfig
@@ -0,0 +1,22 @@
+if BOARD_SIEMENS_MC_EHL5
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select DRIVERS_I2C_RV3028C7
+	select DRIVER_INTEL_I210
+	select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
+	select EHL_TSN_DRIVER
+	select DRIVERS_ETH_PHY_M88E1512
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select TPM_MEASURED_BOOT
+	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd"
+
+config UART_FOR_CONSOLE
+	int
+	default 0
+
+endif # BOARD_SIEMENS_MC_EHL5
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc
new file mode 100644
index 0000000000..6e87f9fc1a
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/Makefile.inc
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
+ramstage-y += mainboard.c
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
new file mode 100644
index 0000000000..f14c225a0b
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
@@ -0,0 +1,250 @@
+chip soc/intel/elkhartlake
+
+	device cpu_cluster 0 on end
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_F"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Disabled"
+
+	# Enable IBECC for the complete memory
+	register "ibecc" = "{
+		.enable = 1,
+		.mode = IBECC_ALL
+	}"
+
+	# USB related UPDs
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC2)"	# X125/X135
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC2)"	# X125/X135
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"	# X145/X155
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"	# X145/X155
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"	# USB Panel
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"	# USB Panel
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port2
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"	# UNUSED
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"	# UNUSED
+
+	# Skip the CPU replacement check
+	register "SkipCpuReplacementCheck" = "1"
+
+	# PCIe root ports related UPDs
+	register "PcieRpEnable[1]" = "1"
+	register "PcieRpEnable[6]" = "1"
+
+	register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
+
+	register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
+
+	# Disable all L1 substates for PCIe root ports
+	register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
+	register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
+
+	# Disable LTR for all PCIe root ports
+	register "PcieRpLtrDisable[1]" = "true"
+	register "PcieRpLtrDisable[6]" = "true"
+
+	# Storage (SDCARD/EMMC) related UPDs
+	register "ScsEmmcHs400Enabled" = "0"
+	register "ScsEmmcDdr50Enabled" = "1"
+	register "SdCardPowerEnableActiveHigh" = "1"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "GPP_G5"
+
+	# LPSS Serial IO (I2C/UART/GSPI) related UPDs
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C4] = PchSerialIoPci,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+		[PchSerialIoIndexI2C6] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
+	}"
+
+	register "SerialIoUartMode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoPci,
+		[PchSerialIoIndexUART2] = PchSerialIoPci,
+	}"
+
+	register "SerialIoUartDmaEnable" = "{
+		[PchSerialIoIndexUART0] = 1,
+		[PchSerialIoIndexUART1] = 1,
+		[PchSerialIoIndexUART2] = 1,
+	}"
+
+	# TSN GBE related UPDs
+	register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps"
+	register "PchTsnGbeSgmiiEnable" = "1"
+	register "PseDmaOwn[0]" = "Host_Owned"
+	register "PseDmaOwn[1]" = "Host_Owned"
+	register "pch_tsn_phy_irq_edge" = "RISING_EDGE"
+	register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE"
+	register "pse_tsn_phy_irq_edge[1]" = "RISING_EDGE"
+
+	register "common_soc_config" = "{
+		.i2c[1] = {
+			.speed = I2C_SPEED_STANDARD,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_STANDARD,
+				.scl_hcnt = 0x1e1,
+				.scl_lcnt = 0x1f4,
+				.sda_hold = 0x64
+			},
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_STANDARD,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_STANDARD,
+				.scl_hcnt = 0x1df,
+				.scl_lcnt = 0x1f4,
+				.sda_hold = 0x64
+			},
+		},
+	}"
+
+	# FIVR related settings
+	register "fivr" = "{
+		.fivr_config_en = true,
+		.vcc_low_high_us = 50,
+	}"
+
+	# Disable L1 prefetcher for real-time demands
+	register "L1_prefetcher_disable" = "true"
+
+	device domain 0 on
+		device pci 00.0 on	end # Host Bridge
+		device pci 02.0 on	end # Integrated Graphics Device
+
+		device pci 14.0 on	end # USB3.1 xHCI
+
+		device pci 15.0 on	end # I2C0
+		device pci 15.1 on	    # I2C1
+			# Enable external RTC chip
+			chip drivers/i2c/rv3028c7
+				register "bus_speed" = "I2C_SPEED_STANDARD"
+				register "set_user_date" = "1"
+				register "user_year" = "04"
+				register "user_month" = "07"
+				register "user_day" = "01"
+				register "user_weekday" = "4"
+				register "bckup_sw_mode" = "BACKUP_SW_LEVEL"
+				register "cap_charge" = "CHARGE_OFF"
+				device i2c 0x52 on end  # RTC RV3028-C7
+			end
+		end
+		device pci 15.2 on	    # I2C2
+		# Add dummy I2C device to limit BUS speed to 100 kHz in OS
+			chip drivers/i2c/generic
+				register "hid" = ""PRP0001""
+				register "speed" = "I2C_SPEED_STANDARD"
+				device i2c 0x7f on end
+			end
+		end
+		device pci 15.3 on	end # I2C3
+
+		device pci 16.0 hidden	end # Management Engine Interface 1
+
+		device pci 19.0 on	end # I2C4
+		device pci 19.1 on	end # I2C5
+		device pci 19.2 on	end # UART2
+
+		device pci 1a.0 on	end # eMMC
+		device pci 1a.1 on	end # SD
+
+		device pci 1c.1 on	end # RP2 (pcie0 single VC)
+		device pci 1c.6 on	end # RP7 (pcie3 multi VC)
+
+		device pci 1d.0 off	end # Intel PSE IPC (local host to PSE)
+		device pci 1d.1 on	    # Intel PSE Time-Sensitive Networking GbE 0
+			# Enable external Marvell PHY 88E1512
+			chip drivers/net/phy/m88e1512
+				register "configure_leds" = "true"
+				# LED[0]: On - 1000 Mbps Link, Off - Else
+				register "led_0_ctrl" = "7"
+				# LED[1]: On - Link, Blink - Activity, Off - No Link
+				register "led_1_ctrl" = "1"
+				# INTn is routed to LED[2] pin
+				register "enable_int" = "true"
+				register "downshift_cnt" = "2"
+				register "force_mos" = "true"
+				register "pmos_val" = "0xF"
+				register "nmos_val" = "0xA"
+				device mdio 0 on    # PHY address
+					ops m88e1512_ops
+				end
+			end
+		end
+		device pci 1d.2 on	    # Intel PSE Time-Sensitive Networking GbE 1
+			# Enable external Marvell PHY 88E1512
+			chip drivers/net/phy/m88e1512
+				register "configure_leds" = "true"
+				# LED[0]: On - 1000 Mbps Link, Off - Else
+				register "led_0_ctrl" = "7"
+				# LED[1]: On - Link, Blink - Activity, Off - No Link
+				register "led_1_ctrl" = "1"
+				# INTn is routed to LED[2] pin
+				register "enable_int" = "true"
+				register "downshift_cnt" = "2"
+				register "force_mos" = "true"
+				register "pmos_val" = "0xF"
+				register "nmos_val" = "0xA"
+				device mdio 1 on    # PHY address
+					ops m88e1512_ops
+				end
+			end
+		end
+
+		device pci 1e.0 on	end # UART0
+		device pci 1e.1 on	end # UART1
+		device pci 1e.4 on	    # PCH Time-Sensitive Networking GbE
+			# Enable external Marvell PHY 88E1512
+			chip drivers/net/phy/m88e1512
+				register "configure_leds" = "true"
+				# LED[0]: On - 1000 Mbps Link, Off - Else
+				register "led_0_ctrl" = "7"
+				# LED[1]: On - Link, Blink - Activity, Off - No Link
+				register "led_1_ctrl" = "1"
+				# INTn is routed to LED[2] pin
+				register "enable_int" = "true"
+				register "downshift_cnt" = "2"
+				device mdio 1 on    # PHY address
+					ops m88e1512_ops
+				end
+			end
+		end
+
+		device pci 1f.0 on	    # eSPI Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.2 hidden	end # Power Management Controller
+		device pci 1f.4	on	end # SMBus
+		device pci 1f.5 on	end # PCH SPI (flash & TPM)
+	end
+end
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c
new file mode 100644
index 0000000000..20a89c64d1
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/gpio.c
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+
+	/* Community 0 - GpioGroup GPP_B */
+	PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1),		/* PMC_VRALERT_N */
+	PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4),		/* ESPI_ALERT0_N */
+	PAD_NC(GPP_B4, NONE),				/* Not connected */
+	PAD_NC(GPP_B9, NONE),				/* Not connected */
+	PAD_NC(GPP_B10, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1),		/* PMC_ALERT_N */
+	PAD_NC(GPP_B14, NONE),				/* Not connected */
+	PAD_NC(GPP_B15, NONE),				/* Not connected */
+	PAD_NC(GPP_B18, NONE),				/* Not connected */
+	PAD_NC(GPP_B19, NONE),				/* Not connected */
+	PAD_NC(GPP_B23, NONE),				/* Not connected */
+
+	/* Community 0 - GpioGroup GPP_T */
+	PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),		/* PSE_GBE0_INT */
+	PAD_CFG_GPO(GPP_T5, 1, DEEP),			/* PSE_GBE0_RST_N */
+	PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),		/* PSE_GBE0_AUXTS */
+	PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),		/* PSE_GBE0_PPS */
+	PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2),		/* SIO_UART0_RXD */
+	PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2),		/* SIO_UART0_TXD */
+
+	/* Community 0 - GpioGroup GPP_G */
+	PAD_NC(GPP_G8, NONE),				/* Not connected */
+	PAD_NC(GPP_G9, NONE),				/* Not connected */
+	PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST),		/* TPM_IRQ_N */
+
+	/* Community 1 - GpioGroup GPP_V */
+	PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1),		/* EMMC_CMD */
+	PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1),		/* EMMC_DATA0 */
+	PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1),		/* EMMC_DATA1 */
+	PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1),		/* EMMC_DATA2 */
+	PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1),		/* EMMC_DATA3 */
+	PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1),		/* EMMC_DATA4 */
+	PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1),		/* EMMC_DATA5 */
+	PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1),		/* EMMC_DATA6 */
+	PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1),		/* EMMC_DATA7 */
+	PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1),		/* EMMC_RCLK */
+	PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1),		/* EMMC_CLK */
+	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),		/* EMMC_RESET */
+
+	/* Community 1 - GpioGroup GPP_H */
+	PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),		/* PSE_GBE1_INT */
+	PAD_CFG_GPO(GPP_H1, 1, DEEP),			/* PSE_GBE1_RST_N */
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),		/* PSE_GBE1_AUXTS */
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),		/* PSE_GBE1_PPS */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),		/* PCIE_CLKREQ4_N */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),		/* PCIE_CLKREQ5_N */
+
+	/* Community 1 - GpioGroup GPP_D */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),		/* PCIE_CLKREQ0_N */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),		/* PCIE_CLKREQ1_N */
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),		/* PCIE_CLKREQ2_N */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),		/* PCIE_CLKREQ3_N */
+
+	/* Community 1 - GpioGroup GPP_U */
+	PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1),		/* GBE_INT */
+	PAD_CFG_GPO(GPP_U1, 1, DEEP),			/* GBE_RST_N */
+	PAD_NC(GPP_U12, NONE),				/* Not connected */
+	PAD_NC(GPP_U13, NONE),				/* Not connected */
+	PAD_NC(GPP_U16, NONE),				/* Not connected */
+	PAD_NC(GPP_U17, NONE),				/* Not connected */
+	PAD_NC(GPP_U18, NONE),				/* Not connected */
+
+	/* Community 2 - GpioGroup DSW */
+	PAD_CFG_NF(GPD1, NONE, PLTRST, NF1),		/* ACPRESENT */
+	PAD_NC(GPD9, NONE),				/* Not connected */
+	PAD_NC(GPD11, NONE),				/* Not connected */
+
+	/* Community 3 - GpioGroup GPP_S */
+	PAD_NC(GPP_S0, NONE),				/* Not connected */
+	PAD_NC(GPP_S1, NONE),				/* Not connected */
+
+	/* Community 3 - GpioGroup GPP_A */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD3 */
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD2 */
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD1 */
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXD0 */
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXCLK */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_TXCTL */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXCLK */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD3 */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD2 */
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD1 */
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD0 */
+	PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD3 */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD2 */
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD1 */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD0 */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXCLK */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXCTL */
+	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXCLK */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXCTL */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD3 */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD2 */
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD1 */
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD0 */
+	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXCTL */
+
+	/* Community 4 - GpioGroup GPP_C */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),		/* PSE_GBE0_MDC */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),		/* PSE_GBE0_MDIO */
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),		/* PSE_GBE1_MDC */
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),		/* PSE_GBE1_MDIO */
+	PAD_NC(GPP_C8, NONE),				/* Not connected */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4),		/* SIO_UART1_RXD */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4),		/* SIO_UART1_TXD */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),		/* GBE_MDIO */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),		/* GBE_MDC */
+
+	/* Community 4 - GpioGroup GPP_F */
+	PAD_NC(GPP_F1, NONE),				/* Not connected */
+	PAD_NC(GPP_F3, NONE),				/* Not connected */
+	PAD_NC(GPP_F8, NONE),				/* Not connected */
+	PAD_NC(GPP_F11, NONE),				/* Not connected */
+	PAD_NC(GPP_F12, NONE),				/* Not connected */
+	PAD_NC(GPP_F13, NONE),				/* Not connected */
+	PAD_NC(GPP_F14, NONE),				/* Not connected */
+	PAD_NC(GPP_F15, NONE),				/* Not connected */
+	PAD_NC(GPP_F16, NONE),				/* Not connected */
+	PAD_NC(GPP_F17, NONE),				/* Not connected */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),			/* LED_BIOS_DONE */
+
+	/* Community 4 - GpioGroup GPP_E */
+	PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),		/* SATA_LED_N */
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),		/* M.2_SSD_SATA_DEVSLP_1 */
+	PAD_NC(GPP_E15, NONE),				/* Not connected */
+	PAD_NC(GPP_E16, NONE),				/* Not connected */
+	PAD_NC(GPP_E18, NONE),				/* Not connected */
+	PAD_NC(GPP_E19, NONE),				/* Not connected */
+	PAD_NC(GPP_E23, NONE),				/* Not connected */
+
+	/* Community 5 - GpioGroup GPP_R */
+	PAD_NC(GPP_R1, NONE),				/* Not connected */
+	PAD_NC(GPP_R3, NONE),				/* Not connected */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c
new file mode 100644
index 0000000000..1121399754
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/mainboard.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <bootstate.h>
+#include <device/pci_ids.h>
+#include <gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+
+#define HOSTCTRL2		0x3E
+#define  HOSTCTRL2_PRESET	(1 << 15)
+#define SD_CAP_BYP		0x810
+#define  SD_CAP_BYP_EN		0x5A
+#define SD_CAP_BYP_REG1		0x814
+#define  SD_CAP_BYP_SDR50	(1 << 13)
+#define  SD_CAP_BYP_SDR104	(1 << 14)
+#define  SD_CAP_BYP_DDR50	(1 << 15)
+
+void variant_mainboard_final(void)
+{
+	struct device *dev;
+
+	/* PIR8 register mapping for PCIe root ports
+	   INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */
+	pcr_write16(PID_ITSS, 0x3150, 0x1032);
+
+	/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
+	dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0);
+	if (dev)
+		pci_write_config8(dev, 0xd8, 0x3e);
+
+	/* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to
+	   layout limitations. */
+	dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
+	if (dev) {
+		uint32_t reg;
+		uint16_t reg16;
+		struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+		if (!res)
+			return;
+		write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN);
+		reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0));
+		/* Disable SDR104 and SDR50 mode while keeping DDR50 mode enabled. */
+		reg &= ~(SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50);
+		reg |= SD_CAP_BYP_DDR50;
+		write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg);
+
+		/* Use preset driver strength from preset value registers. */
+		reg16 = read16(res2mmio(res, HOSTCTRL2, 0));
+		reg16 |= HOSTCTRL2_PRESET;
+		write16(res2mmio(res, HOSTCTRL2, 0), reg16);
+	}
+}
+
+static void finalize_boot(void *unused)
+{
+	/* Set coreboot ready LED. */
+	gpio_output(GPP_F20, 1);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c
new file mode 100644
index 0000000000..7b7dad1129
--- /dev/null
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/memory.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
+
+	.dq_map[DDR_CH0] = {
+		{0xf, 0xf0},
+		{0xf, 0xf0},
+		{0xff, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0}
+	},
+
+	.dq_map[DDR_CH1] = {
+		{0xf, 0xf0},
+		{0xf, 0xf0},
+		{0xff, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0}
+	},
+
+	/*
+	 * The dqs_map arrays map the ddr4 pins to the SoC pins
+	 * for both channels.
+	 *
+	 * the index = pin number on ddr4 part
+	 * the value = pin number on SoC
+	 */
+	.dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6},
+	.dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6},
+
+	/* Baseboard uses 100, 100 and 100 rcomp resistors */
+	.rcomp_resistor = {100, 100, 100},
+
+	.rcomp_targets = {60, 40, 30, 20, 30},
+
+	/* LPDDR4x does not allow interleaved memory */
+	.dq_pins_interleaved = 0,
+
+	/* Baseboard is using config 2 for vref_ca */
+	.vref_ca_config = 2,
+
+	/* Enable Early Command Training */
+	.ect = 1,
+
+	/* Set Board Type */
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memcfg_config(void)
+{
+	return &mc_ehl_lpddr4x_memcfg_cfg;
+}