diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-04-04 14:41:44 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-26 12:11:08 +0000 |
| commit | 3362773a5b6be361b555041b52cd491c4af5ea28 (patch) | |
| tree | 40ceb26a1e8ed97765d0af66844b0ea63ae5389c /src/mainboard/siemens/mc_ehl/variants | |
| parent | 1dff52556ebf0d3c4e6a64a27b233353bd32e89f (diff) | |
mb/siemens/mc_ehl4: Enable SD card
This mainboard has SD slot available and therefore it should be enabled.
Use the same SD card configuration as for mc_ehl2 mainboard.
Change-Id: Icd9b25301311679cf93b05ba83a24e551261a020
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/siemens/mc_ehl/variants')
3 files changed, 43 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc index 2b78a7a75f..d9050f098d 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Makefile.inc @@ -3,5 +3,6 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += mainboard.c all-$(CONFIG_NC_FPGA_POST_CODE) += post.c diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb index 0d1ae7115e..56cfc3bc03 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb @@ -89,6 +89,8 @@ chip soc/intel/elkhartlake register "ScsEmmcHs400Enabled" = "0" register "ScsEmmcDdr50Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" # LPSS Serial IO (I2C/UART/GSPI) related UPDs register "SerialIoI2cMode" = "{ @@ -171,6 +173,7 @@ chip soc/intel/elkhartlake device pci 19.2 on end # UART2 device pci 1a.0 on end # eMMC + device pci 1a.1 on end # SD device pci 1c.0 on end # RP1 (pcie0 single VC) device pci 1c.1 on end # RP2 (pcie0 single VC) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c new file mode 100644 index 0000000000..4584892786 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/mainboard.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <bootstate.h> +#include <device/pci_ids.h> +#include <gpio.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> + +#define HOSTCTRL2 0x3E +#define HOSTCTRL2_PRESET (1 << 15) +#define SD_CAP_BYP 0x810 +#define SD_CAP_BYP_EN 0x5A +#define SD_CAP_BYP_REG1 0x814 +#define SD_CAP_BYP_SDR50 (1 << 13) +#define SD_CAP_BYP_SDR104 (1 << 14) +#define SD_CAP_BYP_DDR50 (1 << 15) + +void variant_mainboard_final(void) +{ + struct device *dev; + + /* Limit SD card speed to DDR50 mode to avoid SDR104/SDR50 modes due to + layout limitations. */ + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + if (dev) { + struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); + clrsetbits32(res2mmio(res, SD_CAP_BYP_REG1, 0), + SD_CAP_BYP_SDR104 | SD_CAP_BYP_SDR50, + SD_CAP_BYP_DDR50); + + /* Use preset driver strength from preset value registers. */ + clrsetbits16(res2mmio(res, HOSTCTRL2, 0), 0, HOSTCTRL2_PRESET); + } +} |