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authorWentao Qin <qinwentao@huaqin.corp-partner.google.com>2024-09-07 15:09:23 +0800
committerKarthik Ramasubramanian <kramasub@google.com>2024-09-10 15:08:48 +0000
commite67aaf2da62db488f6e8dbe046bc844c458b18c0 (patch)
treea5c92880e557739c4eff6385ba1751c644371dd5 /src/mainboard/siemens/mc_apl1
parent45c1e249bf3beb84276f34e958db73380c32b0c8 (diff)
mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU
Check that lnkCap supports ASPM L1, so set it to ASPM_L1 to avoid excessive power consumption. BUG=b:364484621, b:361828368 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage w/o this CL - ``` lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+ ``` w/ this CL - ``` lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl" LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+ ``` Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84241 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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