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author | Werner Zeh <werner.zeh@siemens.com> | 2021-10-29 07:07:14 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-03 08:22:05 +0000 |
commit | e4b2d7da4f8a0d292e194ca281d0c0978fa46606 (patch) | |
tree | c919bf8cd01b4158c0e8f44c5c62e86e22068932 /src/mainboard/siemens/mc_apl1/Kconfig | |
parent | 5cd1871929735f2f05b4509afaa63e1def4f8f16 (diff) |
mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree
On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe
devices. None of the used clock output is dedicated to a special device
(CLK0 drives several devices on the mainboard, CLK1 and CLK2 are
connected to a PCIe switch). Therefore do not use a port mapping of the
clocks to avoid a stopping clock once a device is missing and the
matching root port is disabled. Instead set the mapping to
'PCIE_CLK_FREE' to have a free running clock.
In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.
Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58740
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/mc_apl1/Kconfig')
0 files changed, 0 insertions, 0 deletions