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authorArthur Heymans <arthur@aheymans.xyz>2022-11-07 13:52:11 +0100
committerArthur Heymans <arthur@aheymans.xyz>2023-01-30 10:49:11 +0000
commit69cd729c0cde6f15d1de692f5a2da5d3dfe8ba15 (patch)
tree4f21a3de147f422336545ed3164581b6b80c45d7 /src/mainboard/siemens/chili
parent0a97e466163dda4e55c1eda145646054dcd8dd06 (diff)
mb/*: Remove lapic from devicetree
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/siemens/chili')
-rw-r--r--src/mainboard/siemens/chili/variants/base/devicetree.cb4
-rw-r--r--src/mainboard/siemens/chili/variants/chili/devicetree.cb4
2 files changed, 2 insertions, 6 deletions
diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb
index 81dae2ea1f..8d6c589e4a 100644
--- a/src/mainboard/siemens/chili/variants/base/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb
@@ -7,9 +7,7 @@ chip soc/intel/cannonlake
register "PchHdaDspEnable" = "0"
register "PchHdaAudioLinkHda" = "1"
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+ device cpu_cluster 0 on end
device domain 0 on
device pci 00.0 on end # Host Bridge
diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
index b4d99700ca..cee1967a36 100644
--- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
@@ -7,9 +7,7 @@ chip soc/intel/cannonlake
register "PchHdaDspEnable" = "0"
register "PchHdaAudioLinkHda" = "1"
- device cpu_cluster 0 on
- device lapic 0 on end
- end
+ device cpu_cluster 0 on end
device domain 0 on
device pci 00.0 on end # Host Bridge