diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-07-12 10:53:25 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-14 08:16:07 +0000 |
| commit | 6386cc99736dd7501faeb332d9c231ec685bf898 (patch) | |
| tree | 13be0dde79f6e92d407feedc3fd5a50e47b113eb /src/mainboard/siemens/chili/variants/base | |
| parent | 06bc2c8498d392fe2eb1b9a8f8acfe9609996869 (diff) | |
mb/siemens/chili: Drop ineffective `SaGv` setting
SaGv is only available on ULT/ULX processors, which use PCH-LP. Given
that the Siemens Chili board selects `SOC_INTEL_CANNONLAKE_PCH_H`, it
does not use ULT/ULX processors, and thus does not support SaGv. Drop
the `SaGv` setting from the devicetrees, as it has no effect.
Change-Id: I5be518cce08206ad149efd1665e44a7111b24202
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56205
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/siemens/chili/variants/base')
| -rw-r--r-- | src/mainboard/siemens/chili/variants/base/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 52d8f1ca6a..e49ccd7c78 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -2,7 +2,6 @@ chip soc/intel/cannonlake # FSP configuration - register "SaGv" = "SaGv_Enabled" register "RMT" = "0" register "PchHdaDspEnable" = "0" |