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author | Nicholas Chin <nic.c3.14@gmail.com> | 2024-01-31 22:57:07 -0700 |
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committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-08-26 22:36:34 +0000 |
commit | 5f6dc2867f0b102b7b52c22f4081a540aaf0549f (patch) | |
tree | d3f408da5a8aff6b13885eccac2335efaa483691 /src/mainboard/sapphire | |
parent | ea9be8b505186393620c3a8126ac79eaca9c81d9 (diff) |
mb/dell: Add Latitude E5530 (Ivy Bridge)
Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. I was also sent the VBT binary,
which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
version A21 of the vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/mainboard/sapphire')
0 files changed, 0 insertions, 0 deletions