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| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-06-30 01:30:16 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-21 15:49:09 +0000 |
| commit | 3ba59dc891b4618c50ba398c8395b575315b1442 (patch) | |
| tree | 68c4bfde2f0701d8dd3778bf26093c67f1e01d16 /src/mainboard/sapphire | |
| parent | 5055d88f4054888c50695fc54f8fee4b92dfb726 (diff) | |
mb/intel/ehlcrb: Update FIVR configs
This patch sets the optimized FIVR configs for ehlcrb customized
based on the performance measurements to achieve the better power
savings in sleep states.
- Enable the external V1p05, Vnn, VnnSx rails in S0i3, S3, S4, S5
states.
- Update the supported voltage states.
- Update max supported current, voltage transition time and RFI
spread spectrum.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I1e30ff6d84bfe078fcce0f968fce6aaab7fd575b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/sapphire')
0 files changed, 0 insertions, 0 deletions