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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-16 23:29:23 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 09:00:57 +0000 |
| commit | 6beaef983aee5d886f6f8571855a92d608d98a17 (patch) | |
| tree | 9c7f858bc7baa36d9e18ed84ea61d742559922c2 /src/mainboard/sapphire/pureplatinumh61 | |
| parent | 4821a0e135ff2d60f552203d2724ae2d44850623 (diff) | |
sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree
Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/sapphire/pureplatinumh61')
| -rw-r--r-- | src/mainboard/sapphire/pureplatinumh61/romstage.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index 9a67ab295b..c7d8f0f724 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -24,10 +24,6 @@ void pch_enable_lpc(void) { pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); } |