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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-21 15:04:51 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-01-04 21:23:21 +0000 |
| commit | de7f0736a16edb8d34df6e057b87a0bc1fbf7874 (patch) | |
| tree | 9a412a0102208af69739300b58fbb5c85d46439a /src/mainboard/samsung/lumpy | |
| parent | 1de326460eb240ba9780d8e1a2a2dc73d0f9f347 (diff) | |
mb/*/chromeos.c: Fix PRE_RAM and unify style
Change-Id: I99b9c0452ed0e6d580edb5a4f3317d776085b382
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30399
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/samsung/lumpy')
| -rw-r--r-- | src/mainboard/samsung/lumpy/chromeos.c | 29 |
1 files changed, 13 insertions, 16 deletions
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 0f672b6e5f..bc660b6bdc 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -40,7 +40,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); u8 lid = ec_read(0x83); @@ -88,11 +88,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } @@ -100,11 +98,9 @@ int get_write_protect_state(void) int get_developer_mode_switch(void) { #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1; } @@ -112,19 +108,21 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 2); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); + struct device *dev = pcidev_on_root(0x1f, 2); #endif return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { -#ifdef __PRE_RAM__ u32 flags = 0; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); +#else + struct device *dev = pcidev_on_root(0x1f, 2); +#endif /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -136,8 +134,7 @@ void init_bootmode_straps(void) if (get_gpio(GPIO_DEV_MODE)) flags |= (1 << FLAG_DEV_MODE); - pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); -#endif + pci_write_config32(dev, SATA_SP, flags); } static const struct cros_gpio cros_gpios[] = { |