SNB+MRC boards: Migrate MRC settings to devicetree

For Sandy Bridge boards with MRC raminit support, migrate as much
MRC settings to devicetree as possible, to stop mainboard code from
needlessly overwriting entire PEI data structure, so they will not
interfere with upcoming transition to one standard Haswell way of
providing SPD info to northbridge.

Some exceptions allowed are described below and in code comments.

SPD-related items are kept out of devicetree for now. They will be
migrated (with a different representation) with the Haswell SPD
transition.

google/{butterfly,link,parrot,stout} have max DDR3 frequency set in
pei_data to 1600 (2*800), but in devicetree to 666. The reason for the
difference seems to be problems with native raminit code. These are
converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an
added "fix me" tag. asus/p8x7x-series also needs the same treatment,
based on testing various memory on p8z77-m hardware.

TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested.

Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

2 files changed, 29 insertions, 48 deletions

diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
index 79c182ee91..d2c38f3c10 100644
--- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
+++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
@@ -17,6 +17,29 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x00000ac8"
 	register "gpu_pch_backlight" = "0x13120000"
 
+	register "ec_present" = "1"
+	register "max_mem_clock_mhz" = "800"
+
+	register "usb3.mode" = "3"
+	register "usb3.hs_port_switch_mask" = "0xf"
+	register "usb3.preboot_support" = "1"
+	register "usb3.xhci_streams" = "1"
+	register "usb_port_config" = "{
+		{ 1, 0, 0x0080 },
+		{ 1, 0, 0x0080 },
+		{ 1, 1, 0x0080 },
+		{ 1, 1, 0x0080 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0080 },
+		{ 1, 4, 0x0080 },
+		{ 1, 5, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0080 },
+		{ 1, 6, 0x0080 }, }"
+
 	chip cpu/intel/model_206ax
 		device cpu_cluster 0 on end
 
diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c
index b3378ba428..ffe095d23c 100644
--- a/src/mainboard/roda/rv11/variants/rw11/early_init.c
+++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c
@@ -39,54 +39,12 @@ void bootblock_mainboard_early_init(void)
 
 void mainboard_fill_pei_data(struct pei_data *const pei_data)
 {
-	const struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 1,
-		.gbe_enable = 1,
-		.ddr3lv_support = 0,
-		.max_ddr3_freq = 1600,
-		.usb_port_config = {
-			/* Enabled / OC PIN / Length */
-			{ 1, 0, 0x0080 }, /* P00: 1st (left)     USB3 (OC #0) */
-			{ 1, 0, 0x0080 }, /* P01: 2nd (left)     USB3 (OC #0) */
-			{ 1, 1, 0x0080 }, /* P02: 1st Multibay   USB3 (OC #1) */
-			{ 1, 1, 0x0080 }, /* P03: 2nd Multibay   USB3 (OC #1) */
-			{ 1, 8, 0x0040 }, /* P04: MiniPCIe 1     USB2 (no OC) */
-			{ 1, 8, 0x0040 }, /* P05: MiniPCIe 2     USB2 (no OC) */
-			{ 1, 8, 0x0040 }, /* P06: USB Hub x4     USB2 (no OC) */
-			{ 1, 8, 0x0040 }, /* P07: MiniPCIe 4     USB2 (no OC) */
-			{ 1, 8, 0x0080 }, /* P08: SD card reader USB2 (no OC) */
-			{ 1, 4, 0x0080 }, /* P09: 3rd (right)    USB2 (OC #4) */
-			{ 1, 5, 0x0040 }, /* P10: 4th (right)    USB2 (OC #5) */
-			{ 1, 8, 0x0040 }, /* P11: 3rd Multibay   USB2 (no OC) */
-			{ 1, 8, 0x0080 }, /* P12: misc internal  USB2 (no OC) */
-			{ 1, 6, 0x0080 }, /* P13: misc internal  USB2 (OC #6) */
-		},
-		.usb3 = {
-			.mode =			3,	/* Smart Auto? */
-			.hs_port_switch_mask =	0xf,	/* All four ports. */
-			.preboot_support =	1,	/* preOS driver? */
-			.xhci_streams =		1,	/* Enable. */
-		},
-		.pcie_init = 1,
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xA0, 0xA2, 0xA4, 0xA6};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+	/* TODO: Confirm if need to enable peg10 in devicetree */
+	pei_data->pcie_init = 1;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {