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| author | Jincheng Li <jincheng.li@intel.com> | 2024-03-15 17:17:58 +0800 |
|---|---|---|
| committer | Jérémy Compostella <jeremy.compostella@intel.com> | 2024-03-21 20:37:51 +0000 |
| commit | dc68ada3a066dcdaba3221bf51a4f98c94bf1b98 (patch) | |
| tree | 0a511f822c1ea5007817c248185e7fa7ff549e88 /src/mainboard/roda/rv11/dsdt.asl | |
| parent | e80d06284f4155228f5e9e368a2b65770b1c9c21 (diff) | |
arch/x86: Fix typo for macro CPUID_FEATURE_HTT
Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/mainboard/roda/rv11/dsdt.asl')
0 files changed, 0 insertions, 0 deletions