drivers/generic/ioapic: Drop poor implementation

This disables MP table generation for the affected boards
since interrupt routing entries would now be completely missing.

The mechanism itself is flawed and redundant. The mapping
of integrated PCI devices' INTx pins to IOAPIC pins is
dependent of configuration registers and needs not appear
in the devicetree.cb files at all.

The write_smp_table implementation would skip writing
any entry delivering to destination IOAPIC ID 0. This
does not follow MP table specification.

There were duplicate calls to register_new_ioapic_gsi0(),
with another present under southbridge LPC device.

Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69488
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 16 insertions, 52 deletions

diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb
index cc5d76390f..c9c1896016 100644
--- a/src/mainboard/roda/rk9/devicetree.cb
+++ b/src/mainboard/roda/rk9/devicetree.cb
@@ -23,9 +23,7 @@ chip northbridge/intel/gm45
 	device domain 0 on
 		subsystemid 0x4352 0x8986
 		device pci 00.0 on end # host bridge
-		device pci 02.0 on # VGA
-			ioapic_irq 2 INTA 0x10
-		end
+		device pci 02.0 on end # VGA
 		device pci 02.1 on end # Display
 		device pci 03.0 off end # ME
 		device pci 03.1 off end # ME
@@ -69,62 +67,32 @@ chip northbridge/intel/gm45
 			register "gen1_dec" = "0x000c0601"
 
 			device pci 19.0 off end # LAN
-			device pci 1a.0 on # UHCI
-				ioapic_irq 2 INTA 0x10
-			end
-			device pci 1a.1 on # UHCI
-				ioapic_irq 2 INTB 0x11
-			end
-			device pci 1a.2 on # UHCI
-				ioapic_irq 2 INTC 0x12
-			end
-			device pci 1a.7 on # EHCI
-				ioapic_irq 2 INTC 0x12
-			end
-			device pci 1b.0 on # HD Audio
-				ioapic_irq 2 INTA 0x10
-			end
-			device pci 1c.0 on # PCIe Port #1
-				ioapic_irq 2 INTA 0x10
-			end
+			device pci 1a.0 on end # UHCI
+			device pci 1a.1 on end # UHCI
+			device pci 1a.2 on end # UHCI
+			device pci 1a.7 on end # EHCI
+			device pci 1b.0 on end # HD Audio
+			device pci 1c.0 on end # PCIe Port #1
 			device pci 1c.1 off end # PCIe Port #2
 			device pci 1c.2 off end # PCIe Port #3
 			device pci 1c.3 off end # PCIe Port #4
 			device pci 1c.4 on # PCIe Port #5
-				ioapic_irq 2 INTA 0x10
 				device pci 00.0 on end # Realtek 8168B
 			end
 			device pci 1c.5 off end # PCIe Port #6
-			device pci 1d.0 on # UHCI
-				ioapic_irq 2 INTA 0x10
-			end
-			device pci 1d.1 on # UHCI
-				ioapic_irq 2 INTB 0x11
-			end
-			device pci 1d.2 on # UHCI
-				ioapic_irq 2 INTC 0x12
-			end
-			device pci 1d.7 on # EHCI
-				ioapic_irq 2 INTA 0x10
-			end
+			device pci 1d.0 on end # UHCI
+			device pci 1d.1 on end # UHCI
+			device pci 1d.2 on end # UHCI
+			device pci 1d.7 on end # EHCI
 			device pci 1e.0 on # PCI
-				device pci 03.0 on # TI Cardbus
-					ioapic_irq 2 INTA 0x10
-				end
-				device pci 03.1 on # TI Cardbus
-					ioapic_irq 2 INTB 0x11
-				end
+				# device 03 INTA 0x10, INTB 0x11
+				device pci 03.0 on end # TI Cardbus
+				device pci 03.1 on end # TI Cardbus
 				device pci 03.2 off end # TI FireWire OHC
 				device pci 03.3 off end # unconnected FlashMedia
 				device pci 03.4 off end # unconnected SD-Card
 			end
 			device pci 1f.0 on # LPC bridge
-				chip drivers/generic/ioapic
-					register "have_isa_interrupts" = "1"
-					register "base" = "(void *)0xfec00000"
-					device ioapic 2 on end
-				end
-
 				chip superio/smsc/lpc47n227
 					device pnp 2e.1 on # Parallel port
 						 io 0x60 = 0x378
@@ -142,12 +110,8 @@ chip northbridge/intel/gm45
 					end
 				end
 			end
-			device pci 1f.2 on # SATA/IDE 1
-				ioapic_irq 2 INTB 0x11
-			end
-			device pci 1f.3 on # SMBus
-				ioapic_irq 2 INTC 0x12
-			end
+			device pci 1f.2 on end # SATA/IDE 1
+			device pci 1f.3 on end # SMBus
 			device pci 1f.5 off end # SATA/IDE 2
 			device pci 1f.6 off end # Thermal
 		end