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authorLean Sheng Tan <sheng.tan@9elements.com>2023-03-13 14:59:36 +0100
committerLean Sheng Tan <sheng.tan@9elements.com>2023-03-15 14:44:24 +0000
commit742b65bdf6e0fc6dd46b30c8c91eae5d1efff828 (patch)
tree39586814a3e5a74b79e5fdf0431b0869b3d278cf /src/mainboard/razer
parent41546a524091165d04f0a91bba431f3245877bf2 (diff)
soc/intel/tigerlake: Select `X86_CLFLUSH_CAR` config
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I97c8c07db9b44aa89b433e7962ec77c8501ecaa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com>
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