diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-10 01:24:11 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:13:23 +0000 |
| commit | 97c5464443306f26b61cec3a0f50108a5c06b7ef (patch) | |
| tree | f085457907ad200a0d9d9be8a07c937e755fae91 /src/mainboard/razer | |
| parent | 19c2ce7639d55908d210782ae5a0315396cc7eaf (diff) | |
skylake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on nami system
Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/razer')
| -rw-r--r-- | src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index b55ef41f2d..7d54d33d8e 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -170,10 +170,11 @@ chip soc/intel/skylake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC? # PL1 override 25W - register "tdp_pl1_override" = "25" - # PL2 override 44W - register "tdp_pl2_override" = "44" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 44, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" |