From 97c5464443306f26b61cec3a0f50108a5c06b7ef Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Sun, 10 May 2020 01:24:11 +0530 Subject: skylake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Skylake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on nami system Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45 Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/mainboard/razer') diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index b55ef41f2d..7d54d33d8e 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -170,10 +170,11 @@ chip soc/intel/skylake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC? # PL1 override 25W - register "tdp_pl1_override" = "25" - # PL2 override 44W - register "tdp_pl2_override" = "44" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 44, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" -- cgit v1.2.3