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authorFelix Singer <felixsinger@posteo.net>2020-07-29 21:44:36 +0200
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-08-08 12:00:23 +0000
commit52919523c14396a8a5dffa34afe40b24b7d68dfc (patch)
tree7a20492ce7ac016462b6bf4923741fdb9a4b38a0 /src/mainboard/razer/blade_stealth_kbl
parent0da148e326f140ebdb9ef26e864ef453bc36bdfa (diff)
soc/intel/skylake: Enable SDXC depending on devicetree configuration
Currently, SDXC gets enabled by the option ScsSdCardEnabled, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SDXC controller. All corresponding mainboards were checked if the devicetree configuration matches the ScsSdCardEnabled setting, and missing entries were added. Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/mainboard/razer/blade_stealth_kbl')
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index 4306da6b36..6217de5097 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -37,7 +37,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
- register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
@@ -228,6 +227,7 @@ chip soc/intel/skylake
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.0 on end # Serial IO UART0
+ device pci 1e.6 off end # SDXC
device pci 1f.0 on # LPC
chip drivers/pc80/tpm
device pnp 0c31.0 on end