mb/razer: Make use of chipset devicetree

Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.

Built razer/blade_stealth_kbl with BUILD_TIMELESS=1 and the resulting
binary remains the same.

Change-Id: I0ffda6ee37e146e894a271c553e998a269c19294
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

1 files changed, 17 insertions, 44 deletions

diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index f88c99d0c7..132316481d 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -170,16 +170,12 @@ chip soc/intel/skylake
 
 	device cpu_cluster 0 on end
 	device domain 0 on
-		device pci 00.0 on  end # Host Bridge
-		device pci 02.0 on  end # Integrated Graphics Device
-		device pci 04.0 on  end # Thermal Subsystem
-		device pci 08.0 off end # Gaussian Mixture Model
-		device pci 14.0 on  end # USB xHCI
-		device pci 14.1 off end # USB xDCI (OTG)
-		device pci 14.2 on  end # Thermal Subsystem
-		device pci 14.3 off end # Camera
-		device pci 15.0 on  end # I2C Controller #0
-		device pci 15.1 on
+		device ref igpu		on  end
+		device ref sa_thermal	on  end
+		device ref south_xhci	on  end
+		device ref thermal	on  end
+		device ref i2c0		on  end
+		device ref i2c1		on
 			chip drivers/i2c/hid
 				register "generic.hid" = ""PNP0C50""
 				register "generic.desc" = ""Synaptics Touchpad""
@@ -188,33 +184,13 @@ chip soc/intel/skylake
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 0x2c on end
 			end
-		end # I2C Controller #1
-		device pci 15.2 off end # I2C Controller #2
-		device pci 15.3 off end # I2C Controller #3
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT Redirection
-		device pci 16.4 off end # Management Engine Interface 3
-		device pci 17.0 off end # SATA
-		device pci 19.0 on  end # I2C Controller #4
-		device pci 19.1 off end # I2C Controller #5
-		device pci 19.2 off end # UART #2
-		device pci 1c.0 on  end # PCI Express Port 1
-		device pci 1c.1 off end # PCI Express Port 2
-		device pci 1c.2 off end # PCI Express Port 3
-		device pci 1c.3 off end # PCI Express Port 4
-		device pci 1c.4 on  end # PCI Express Port 5
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
-		device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
-		device pci 1d.3 off end # PCI Express Port 12
-		device pci 1e.0 off end # Serial IO UART0
-		device pci 1e.6 off end # SDXC
-		device pci 1f.0 on # LPC
+		end
+		device ref heci1	on  end
+		device ref uart2	on  end
+		device ref pcie_rp1	on  end
+		device ref pcie_rp5	on  end
+		device ref pcie_rp9	on  end
+		device ref lpc_espi	on
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end
 			end
@@ -236,12 +212,9 @@ chip soc/intel/skylake
 				device pnp 6e.18 off end
 				device pnp 6e.19 off end
 			end	#superio/ite/it8528e
-		end # LPC Bridge
-		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
-		device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 off end # GbE
+		end
+		device ref hda		on  end
+		device ref smbus	on  end
+		device ref fast_spi	on  end
 	end
 end