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authorElyes Haouas <ehaouas@noos.fr>2022-11-18 15:21:03 +0100
committerElyes Haouas <ehaouas@noos.fr>2023-01-30 22:11:50 +0000
commit486240fc7d2f1f8fc5bac2614d5f4139ab8d4ea3 (patch)
tree23e4c847aa743f03125518e6cf103c072fe3cb28 /src/mainboard/purism/librem_skl
parentf58abca47a48c3f3e6cee2599b1fcb7619865169 (diff)
src/mainboard: Remove unnecessary space after casts
Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69815 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Diffstat (limited to 'src/mainboard/purism/librem_skl')
-rw-r--r--src/mainboard/purism/librem_skl/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c
index 604db60e61..2b35fc2017 100644
--- a/src/mainboard/purism/librem_skl/romstage.c
+++ b/src/mainboard/purism/librem_skl/romstage.c
@@ -31,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
mem_cfg->DqPinsInterleaved = TRUE;
mem_cfg->CaVrefConfig = 2;
mem_cfg->MemorySpdDataLen = blk.len;
- mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
/* Enable and set SATA HSIO adjustments for ports 0 and 2 */
mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1;