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authorMatt DeVillier <matt.devillier@puri.sm>2020-04-29 17:45:57 -0500
committerPatrick Georgi <pgeorgi@google.com>2020-05-04 18:52:28 +0000
commit939cabfae43661b75fb109bd8f280aee0a99ec7e (patch)
tree0780f990768d403ed5857924d0b5a39831bf0984 /src/mainboard/purism/librem_skl/variants/librem13v2
parent13dee2a9113bfbcce9ae8b302a759af062ecf486 (diff)
mb/purism/librem_skl: drop SataSpeedLimit restriction
SataSpeedLimit was set to 3Gbps to work around issues which are now known to be the result of incorrect FSP behavior. Since SataPwrOptEnable is now set at the SoC level and ensures the SIR registers are correctly programmed, we can re-enable 6Gbps operation without errors. Test: build/boot Librem 13v2 with both m.2 and 2.5" SATA drives, check dmesg for errors. Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40909 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/purism/librem_skl/variants/librem13v2')
-rw-r--r--src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
index 6c55af66cc..b15dc2df2e 100644
--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
@@ -54,7 +54,6 @@ chip soc/intel/skylake
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[2]" = "0"
- register "SataSpeedLimit" = "2"
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"