diff options
| author | Matt DeVillier <matt.devillier@puri.sm> | 2020-04-30 14:47:26 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-04 20:49:51 +0000 |
| commit | 2b2f67fb7e3e6e7dd6360540c16a2cf8e52b7175 (patch) | |
| tree | 7a136717bdcf604af6aa10f306efcf4a8bed6ec0 /src/mainboard/purism/librem_skl/variants/librem13 | |
| parent | 57e37c58639f01b5249628425323f69770606fbf (diff) | |
mb/purism/librem_skl: rename variant directories
Since the same variant dirs are used by multiple versions of the
same board, drop the v2/v3 labels.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Id913e31ab52043e49769be9d3ebf6e71ecb0c856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/mainboard/purism/librem_skl/variants/librem13')
| -rw-r--r-- | src/mainboard/purism/librem_skl/variants/librem13/board_info.txt | 9 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb | 17 |
2 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/purism/librem_skl/variants/librem13/board_info.txt b/src/mainboard/purism/librem_skl/variants/librem13/board_info.txt new file mode 100644 index 0000000000..fb0dd0bec8 --- /dev/null +++ b/src/mainboard/purism/librem_skl/variants/librem13/board_info.txt @@ -0,0 +1,9 @@ +Vendor name: Purism +Board name: Librem 13 v2 +Board URL: https://puri.sm/librem-13/ +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb new file mode 100644 index 0000000000..18ce220753 --- /dev/null +++ b/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb @@ -0,0 +1,17 @@ +chip soc/intel/skylake + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD + + # OC1 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + + device domain 0 on end +end |