purism/librem13v2: convert to variant setup

Convert the Purism Librem13v2 board to a variant setup,
in preparation of adding the librem15v3 as a new variant.
The 13v2 and 15v3 are nearly identical, so this minimizes new
code to add support for the latter.

Change-Id: I5d648cdb8f63c03de5474253203b3d0853673294
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22047
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 46 insertions, 0 deletions

diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c
new file mode 100644
index 0000000000..48db885075
--- /dev/null
+++ b/src/mainboard/purism/librem_skl/romstage.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2017 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include "pei_data.h"
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg;
+	struct spd_block blk = {
+		.addr_map = { 0x50 },
+	};
+
+	mem_cfg = &mupd->FspmConfig;
+
+	get_spd_smbus(&blk);
+	dump_spd_info(&blk);
+	assert(blk.spd_array[0][0] != 0);
+
+	mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+	mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+	mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+	mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+	mem_cfg->DqPinsInterleaved = TRUE;
+	mem_cfg->MemorySpdDataLen = blk.len;
+	mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+}