diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-23 20:41:09 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-30 00:43:51 +0000 |
| commit | 34672f2bc4e8378d3c24bc026022c36cef261ab1 (patch) | |
| tree | cc5fb1d711f1c84993f224b8c7c6ef7a738b075a /src/mainboard/purism/librem_bdw/variants/librem13v1 | |
| parent | 5e60637ef6ca64bedacbdd5aad1d1a7a85d67c05 (diff) | |
mb/purism/librem_bdw: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical.
Change-Id: I0fe6de35f7471ce173df40db1444153623544f00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46705
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/purism/librem_bdw/variants/librem13v1')
| -rw-r--r-- | src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index d3d0ae72d0..237e6979ec 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell - # Port 0 is HDD - # Port 3 is M.2 NGFF - register "sata_port_map" = "0x9" + device domain 0 on +# chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 3 is M.2 NGFF + register "sata_port_map" = "0x9" - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "9" - register "sata_port3_gen3_dtle" = "9" + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "9" + register "sata_port3_gen3_dtle" = "9" - device domain 0 on - device pci 1c.2 on end # PCIe Port #3 - LAN + device pci 1c.2 on end # PCIe Port #3 - LAN +# end end end |