diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-07-19 11:59:50 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-08-28 00:35:27 +0000 |
| commit | 8c4d7e7e9112d079687a1679799c659b576e96cb (patch) | |
| tree | bf591eb03470ed8b79ea9a524827ecdf64344c9b /src/mainboard/protectli | |
| parent | 9c8debf6b53c451559f4372ab9c7682b860f8fd6 (diff) | |
tree: Use boolean for "eist_enable"
Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Diffstat (limited to 'src/mainboard/protectli')
| -rw-r--r-- | src/mainboard/protectli/vault_cml/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/protectli/vault_ehl/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/protectli/vault_kbl/devicetree.cb | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 14e604890e..01c5df7724 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" register "cpu_pl2_4_cfg" = "baseline" diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index bfb7937c71..df0dbdfdb0 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -8,7 +8,7 @@ chip soc/intel/elkhartlake }" register "SaGv" = "SaGv_Enabled" - register "eist_enable" = "1" + register "eist_enable" = "true" # Enable lpss s0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 3369502b0b..9b0357f654 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -12,7 +12,7 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "eist_enable" = "1" + register "eist_enable" = "true" # Disable DPTF register "dptf_enable" = "0" |